Read-Once Memory Circuit With Destructive Flip-Flop Readout
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Solution Overview
Problem
Existing memory technologies do not effectively address the need for a read-once or destructive readout memory that erases data upon reading, which is crucial for secure storage and non-reversible operations like encryption and one-time use information.
Innovation Solution
A volatile memory circuit comprising flip-flops and logic circuitry that combines outputs to generate a readout while resetting the memory cell upon reading, ensuring data is erased after output, utilizing XOR, AND, and NAND logic gates to manage readout and programming control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory technologies are used, then data can be stored and retrieved multiple times, but the data cannot be automatically erased upon reading, which compromises security for one-time use information
Solution Approach 1:
The memory cell is segmented into two separate flip-flops (first and second flip-flops) with distinct functions. The first flip-flop stores the data bit, while the second flip-flop tracks the read state. This segmentation allows the circuit to differentiate between read and write operations, enabling automatic erasure upon reading without compromising overall memory functionality.
Solution Approach 2:
The second flip-flop acts as an intermediary element that mediates between the data storage function and the readout control. It receives the readout control signal and the data from the first flip-flop, then generates the output while triggering the erasure mechanism. This intermediary structure enables the complex read-once behavior without requiring complete redesign of the memory cell.
2Reliability
If a read-once memory structure is implemented using additional control circuitry, then data erasure upon reading is achieved, but the memory cell complexity increases
Solution Approach 1:
The second flip-flop serves multiple functions: it acts as a read state tracker, an output buffer, and a trigger for the erasure mechanism. By making this element multi-functional, the patent reduces the need for additional dedicated circuitry for each function, thereby limiting the increase in overall device complexity while achieving data integrity through automatic erasure.
Solution Approach 2:
The patent merges the readout control logic, data output logic, and erasure trigger logic into a unified structure using the second flip-flop and associated logic gates. Instead of having separate circuits for each function, they are combined in a way that the second flip-flop's state transitions naturally trigger the erasure of the first flip-flop, reducing the total component count compared to a fully separate implementation.
3Reliability
If two flip-flops are used per memory cell to enable read-once functionality, then data can be securely erased after reading, but the area occupied by each memory cell increases
Solution Approach 1:
The patent applies local quality by giving each flip-flop a specific, localized function within the memory cell. The first flip-flop is dedicated to data storage with simple write capability, while the second flip-flop is dedicated to read control and state tracking. This functional specialization allows each sub-component to be optimized for its specific purpose, potentially reducing the area each flip-flop requires compared to a more complex single-unit design.
Data Source
AI summary
A volatile memory circuit includes a first flip-flop, a second flip-flop having a set input coupled to an output of the first flip-flop. Logic circuitry of the memory circuit logically combines an output of the second flip-flop and information representative of the output of the first flip-flop to generate an output of the memory circuit. In response to a read command, the first flip-flop is reset and content of the second flip-flop is output by the circuit.