Read Preamble Data Training Pattern Memory Controller Timing
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Solution Overview
Problem
In high-speed serial memory interfaces, the shrinking clock period and relatively constant clock to data valid time and data hold time specifications create challenges for successful data capture, particularly as the data valid period collapses with increasing clock frequencies, making it difficult to determine the optimal capture point for data in memory systems.
Innovation Solution
The implementation of a read preamble with a data training pattern during dummy clock cycles allows the host controller to determine the optimal capture point by comparing the received training pattern with an expected pattern, enabling reliable data capture even at higher clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to improve data throughput, then productivity increases, but the data valid period collapses making data capture unreliable
Solution Approach 1:
The patent applies preliminary action by transmitting a training pattern before the actual data during dummy clock cycles. This training pattern allows the host controller to pre-determine the optimal capture point by comparing received bits with expected values, establishing timing alignment before high-speed data transfer begins. This resolves the contradiction by enabling reliable capture at high clock frequencies through advance timing calibration.
Solution Approach 2:
The patent implements feedback by using the training pattern comparison results to adjust and determine the optimal capture point. The host controller compares received training pattern bits with expected values and uses this feedback information to identify the precise timing alignment needed for subsequent data capture. This feedback mechanism ensures reliable data capture even as clock frequencies increase and timing margins shrink.
2Productivity
If clock period is reduced to increase clock frequency, then productivity increases, but the time available for data capture decreases
Solution Approach 1:
The training pattern is transmitted during dummy clock cycles before actual data transfer, performing the timing calibration action in advance. This preliminary timing establishment allows the system to capture data at optimal points even when the data valid period becomes very short at high clock frequencies, effectively decoupling the clock period reduction from data capture time availability.
Solution Approach 2:
The system uses itself to determine the optimal capture point by comparing its own transmitted training pattern with what is received. The host controller performs self-calibration by analyzing the training pattern feedback, identifying timing skew and determining the best capture moment without requiring external intervention or additional hardware, enabling reliable operation at reduced clock periods.
3Measurement precision
If dummy clock cycles are used to transmit training pattern, then measurement precision of capture point improves, but loss of time increases
Solution Approach 1:
The patent uses a training pattern of limited length (e.g., 3-7 bits) transmitted during a small number of dummy clock cycles. This partial action provides sufficient information for the host controller to determine the optimal capture point through comparison with expected values, achieving adequate measurement precision without excessive time loss. The training pattern length is optimized to balance alignment precision against the time cost of dummy cycles.
Data Source
AI summary
A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.