Read-Preferred SRAM Cell Design for Improved Read Margins
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Solution Overview
Problem
Existing SRAM cells face reduced read and write margins due to scaling issues, leading to errors from static noise, and conventional solutions complicate circuits and slow down operations by requiring dynamic power for both read and write operations.
Innovation Solution
A read-preferred SRAM cell design with asymmetric MOS devices and distinct bitline voltages for read and write operations, utilizing static power for reads and dynamic power for writes, with optimized drive current ratios and asymmetric implantation regions to enhance read margins while maintaining or improving write margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic power is provided for both read and write operations to improve read and write margins, then the read and write margins are improved, but the circuit complexity increases and operation speed decreases
Solution Approach 1:
The patent segments the power supply strategy by providing static power for read operations and dynamic power for write operations. This divides the previously unified power supply approach into two distinct modes, allowing optimization for each operation type independently while avoiding the need for complex dynamic power circuits during read operations.
Solution Approach 2:
The patent implements dynamic power supply voltages for write operations (increasing bitline voltage and reducing power supply voltage VDD) while using static power for read operations. This dynamic adjustment of power parameters only when needed (during writes) improves write margin without permanently increasing circuit complexity or slowing down read operations.
2Reliability
If dynamic power is provided for both read and write operations to improve read and write margins, then the read and write margins are improved, but the operation speed decreases
Solution Approach 1:
The patent applies periodic action by switching between static power mode (for reads) and dynamic power mode (for writes). The dynamic power parameters are activated only during write operations and returned to static levels for read operations, preventing continuous slowdown while maintaining improved margins when needed.
Solution Approach 2:
The patent uses dynamic power supply adjustments (bitline voltage increase and VDD reduction) specifically during write operations to improve write margin, while read operations use static power for faster execution. This dynamic switching ensures speed is maintained during reads while reliability is improved during writes.
3Area of moving object
If scaling is applied to reduce device size, then the device density increases, but the read and write margins are reduced
Solution Approach 1:
The patent compensates for scaling-induced margin degradation by changing power supply parameters dynamically. During write operations, bitline voltage is increased and power supply voltage VDD is reduced, creating favorable voltage conditions that restore write margin despite smaller device dimensions. Read operations use static power to maintain speed while accepting scaled dimensions.
Data Source
AI summary
A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM cell; and applying a static power to perform a read operation on the SRAM cell.