Memory Controller ECC Selection Using Read Quality Status
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Solution Overview
Problem
Existing memory controller systems face challenges in balancing error correction efficiency with data access speed, particularly in flash memory devices, where error correction techniques like LDPC and TCM can slow down data retrieval.
Innovation Solution
The implementation of a memory controller that uses a status indication command to determine the quality of data and applies appropriate error correction techniques, including hard and soft data processing, to rapidly correct errors, and employs a read quality status command to streamline error correction and reduce read times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction techniques like LDPC and TCM are applied to improve data reliability, then bit error rates are reduced, but data access speed deteriorates
Solution Approach 1:
The patent implements dynamic error correction by selecting between different ECC techniques (ECC36, ECC72, syndromed ECC) based on the detected data quality status. When read disturbances are detected, more robust error correction is applied; when data quality is high, lighter correction is used, thus adapting the error correction strength to actual needs and improving overall access speed while maintaining reliability.
Solution Approach 2:
The system changes the error correction parameters dynamically based on read quality indicators. The memory controller adjusts which ECC algorithm is applied depending on the detected data quality status, effectively changing the correction parameters (algorithm type, strength) to optimize the balance between reliability and speed for different data conditions.
2Measurement precision
If comprehensive error correction is applied to all data reads, then data accuracy is improved, but read time increases
Solution Approach 1:
The patent applies partial error correction action by using read quality status to determine whether full error correction is necessary. When the status indication shows high data quality, minimal or no error correction is applied; when disturbances are detected, comprehensive correction is applied. This partial action approach maintains accuracy when needed while reducing time loss when not needed.
Solution Approach 2:
The system uses feedback from read quality status indications to control the error correction process. The memory controller receives status information about data quality and uses this feedback to decide whether to apply error correction and which type of correction to use, creating a closed-loop system that optimizes both accuracy and read time based on actual data conditions.
Data Source
AI summary
A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).