Read Refresh in Nonvolatile Memory for Read Disturb Protection
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Solution Overview
Problem
Conventional non-volatile memory devices, such as NAND, suffer from low bandwidth and high power consumption, making them unsuitable alternatives to high bandwidth volatile memory devices like DRAM for applications requiring high data access rates and low power consumption.
Innovation Solution
Implementing a high bandwidth flash (HBF) package with read refresh techniques that relocate data from programmed memory blocks to spare blocks and erase the original blocks to maintain threshold voltage margins, thereby enhancing bandwidth and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional NAND memory is used, then cost is reduced, but bandwidth is insufficient and power consumption is too high
Solution Approach 1:
The memory device is divided into multiple memory blocks, with one block designated as a spare block. This segmentation allows the system to perform read operations on multiple blocks simultaneously while maintaining a reserved block for refresh operations, thereby increasing overall bandwidth without proportionally increasing power consumption.
Solution Approach 2:
The patent implements a read refresh mechanism where data is proactively relocated from heavily read blocks to the spare block before read disturb causes data errors. This preliminary action prevents data corruption and maintains threshold voltage margins, enabling sustained high-bandwidth operation without requiring excessive power for error correction.
2Speed
If read operations are performed repeatedly on the same memory block, then data access speed is maintained, but read disturb causes data errors
Solution Approach 1:
The system proactively relocates data from frequently accessed memory blocks to the spare block based on read count thresholds or time intervals. This preliminary refresh action prevents read disturb from causing data errors, maintaining both high data access speed and data accuracy by ensuring data integrity before errors occur.
Solution Approach 2:
The patent implements a feedback mechanism that monitors read operations on each memory block. When a block exceeds a predetermined read threshold or time interval, the system triggers a refresh operation to relocate data to the spare block. This feedback-based approach dynamically adjusts refresh timing to maintain data reliability while minimizing the impact on access speed.
3Reliability
If data is relocated frequently to maintain threshold voltage margins, then data reliability is improved, but bandwidth is reduced
Solution Approach 1:
By dividing the memory into multiple blocks with one dedicated spare block, the system can perform read operations on multiple active blocks simultaneously while refreshing only the spare block. This segmentation allows data reliability to be maintained through selective refresh operations without significantly impacting overall bandwidth, as the refresh operations on a single block do not halt reads from other blocks.
Data Source
AI summary
The memory device includes a plurality of programmed memory blocks containing data and at least one spare memory block that does not contain data. The memory device also includes control circuitry that is configured to perform a plurality of read operations on the programmed memory blocks. Without having reprogrammed the memory cells of any of the plurality of programmed memory blocks, the circuitry is configured to detect a trigger event. In response to detecting the trigger event, the circuitry is configured to relocate data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block so that the at least one spare memory block becomes a programmed memory block and then erase the selected memory block so that the selected memory block becomes a new spare memory block.