Read Retry Scratch Space for NAND Flash Error Recovery
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Solution Overview
Problem
Traditional memory devices face challenges with excessive error correction code (ECC) errors during read operations, leading to corrupted data and increased latency, particularly due to read disturb errors and bit error rates in NAND flash memory systems.
Innovation Solution
The implementation of Read Retry Scratch Space features allows for custom, optimized read retry settings to be loaded into a memory device's scratch space, enabling flexible recovery from ECC errors without disrupting existing factory settings, thereby reducing failed reads and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional read operations are performed in NAND flash memory, then data can be read from memory cells, but excessive ECC errors occur leading to corrupted data and increased latency
Solution Approach 1:
The patent applies preliminary action by pre-loading multiple read retry offset settings (e.g., OFFSET_0 through OFFSET_7) into the memory device's internal registers before actual read operations occur. When read disturb errors are detected, the system can immediately switch to pre-configured offset values without performing time-consuming recalibration, thereby reducing read latency while maintaining data reliability
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting read voltage offsets based on detected error patterns. The memory device allows programming of multiple offset values that modify the read voltage parameters, enabling the system to adapt to different read disturb conditions and bit error rates by selecting appropriate offset values, thus improving read reliability without permanent disruption to factory settings
2Reliability
If read retry features are implemented to recover from ECC errors, then data recovery improves, but factory settings are disrupted and recalibration is required
Solution Approach 1:
The patent applies segmentation by separating read retry functionality into distinct, independently configurable offset settings (OFFSET_0 through OFFSET_7). Each offset value represents a discrete read retry configuration that can be programmed without affecting others. This segmentation allows the system to implement robust error recovery while preserving factory default settings, as each offset can be selectively activated based on error conditions without disrupting the overall factory configuration
Solution Approach 2:
The patent implements copying by creating duplicate copies of read retry offset values in the memory device's internal registers. Instead of modifying the single factory setting, the system copies the factory offset value and creates multiple backup offset versions (OFFSET_1 through OFFSET_7) that can be programmed with adjusted values. This copying mechanism enables read retry operations to be performed using replicated offset data, leaving the original factory settings intact and undisturbed
3Reliability
If multiple read retry offset settings are programmed into the memory device, then recovery from read disturb errors improves, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single memory device architecture that can perform multiple functions: it can operate with factory default offset settings for normal reads, switch to pre-programmed offset values for read retry operations, and accommodate different offset configurations (OFFSET_0 through OFFSET_7) within the same device. This multi-functional design enables robust error recovery without requiring multiple specialized devices or complex external calibration systems, thereby improving reliability while managing device complexity through integrated multi-functionality
Data Source
AI summary
Devices and techniques to recover data from a memory device are disclosed, including recovering data corresponding to a detected error in data stored on a memory array corresponding to a memory operation using one of a set of read offset values and loading the one of the set of read offset values used to recover data corresponding to the detected error in a temporary storage of the memory array as a custom read offset value for a subsequent memory operation. The temporary storage of the memory array can include a scratch space of the memory array separate from read retry offset registers of the memory device.