Internal Read Signal Generator for Semiconductor Memory
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Solution Overview
Problem
High-frequency operations in semiconductor memory devices often result in malfunction due to excessive delay time differences between clock signals, leading to improper generation of internal read signals, particularly for burst lengths greater than 4, where the delay time exceeds the clock period, causing issues in signal synchronization and output timing.
Innovation Solution
Incorporating a first delay means to adjust the clock signal and a second delay means to synchronize and combine internal read signals, ensuring the rising edge of the output signal aligns with the clock period, thereby compensating for additional delays and maintaining signal integrity at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay time difference between clock signals is increased to accommodate burst lengths greater than 4, then the semiconductor memory device can handle longer burst operations, but the delay time exceeds the clock period causing signal synchronization failures and malfunctions at high frequencies
Solution Approach 1:
The patent divides the delay function into two separate delay circuits: a first delay circuit that introduces a fixed delay time, and a second delay circuit that dynamically adjusts delay based on clock period. This segmentation allows the system to achieve long burst length capability while maintaining synchronization reliability by preventing any single delay circuit from causing excessive total delay.
Solution Approach 2:
The patent employs dynamic adjustment of delay parameters through the second delay circuit, which modifies its delay amount based on the clock period. This dynamic behavior allows the system to adapt to varying operating conditions and maintain proper signal synchronization across different burst lengths without fixed excessive delays.
2Adaptability or versatility
If the delay time is increased to support burst lengths greater than 4, then longer burst operations become possible, but the output signal timing becomes misaligned with the clock period at high frequencies
Solution Approach 1:
The patent segments the delay function between two circuits with different roles: the first delay circuit provides a base delay for burst length >4 operations, while the second delay circuit fine-tunes the timing to ensure output signals align precisely with clock periods, thereby maintaining timing precision across varying burst lengths.
Solution Approach 2:
The patent changes delay parameters dynamically through the second delay circuit, which adjusts its delay amount based on the clock period. This parameter adjustment ensures that the total delay remains compatible with the clock timing, preventing output signal misalignment even when supporting longer burst operations.
3Device complexity
If a single delay circuit is used to generate internal read signals for burst lengths greater than 4, then the circuit structure remains simple, but the delay time difference exceeds the clock period causing malfunction at high frequencies
Solution Approach 1:
The patent segments the delay function into two separate delay circuits rather than using a single complex delay circuit. This segmentation distributes the delay functionally, allowing each circuit to handle specific aspects of timing without creating excessive total delay that would cause high-frequency malfunctions.
Solution Approach 2:
The second delay circuit acts as an intermediary that receives the output from the first delay circuit and further adjusts the timing. This intermediary function ensures that the final output signal timing remains compatible with the clock period, preventing high-frequency operation failures while supporting burst lengths greater than 4.
Data Source
AI summary
The internal read signal generator according to the present invention includes: a first delay unit for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal; a signal transfer unit for transferring the input signal in synchronization with the delayed clock signal of the first delay unit; a second delay unit for delaying an output signal of the signal transfer unit; and an output unit for combining the input signal and an output signal of the second delay unit, wherein an amount of the delay of the second delay unit is determined in order that a rising edge of an output signal of the output unit has a period of the clock signal.