Read Snapshot and In-Place Write Update for Multi-Core Data Movement

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Solution Overview

Problem

Modern processors face performance delays and increased energy consumption due to significant data sharing and movement between multiple cores, which current solutions fail to adequately address, leading to inefficiencies in data parallelism and cache coherency traffic.

Innovation Solution

The introduction of new instructions, such as MOVGET and MOVPUT, enables read snapshot and in-place write update operations that allow data to be sourced or updated without altering the cache line's coherency state or location, optimizing data movement and reducing unnecessary data transfers and energy consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is shared and moved between multiple cores using conventional cache coherency protocols, then data consistency is maintained, but performance delays and energy consumption increase significantly

Engineering Contradiction:
Improvedata consistencyVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent uses snapshot copies of cache lines to allow multiple cores to access data without requiring full cache coherency protocols. Instead of maintaining consistent state across all caches, the system creates snapshot copies that can be read without invalidating other copies, reducing coherency traffic and energy consumption while maintaining data consistency for the duration of the snapshot.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent segments data access into snapshot reads and in-place writes, separating the read and write operations. Snapshot reads create a snapshot of the cache line without requiring exclusive access, while in-place writes allow writers to update data without invalidating reader copies. This segmentation allows concurrent access patterns that reduce coherency protocol overhead.

Inventive Principle:
Principle #1Segmentation

2Reliability

If conventional cache coherency protocols are used for data movement, then data consistency is ensured, but cache hierarchy changes and coherency traffic increase

Engineering Contradiction:
Improvedata consistencyVSAvoidcoherency traffic
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent creates snapshot copies of cache lines that can be shared among multiple cores without requiring invalidation or state changes in the original cache. This copying mechanism allows readers to access data without triggering coherency protocols, significantly reducing coherency traffic while maintaining consistency through the snapshot mechanism.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The snapshot mechanism acts as an intermediary between readers and writers. Instead of direct cache coherency protocols managing all access, the snapshot serves as a mediator that allows readers to access a stable copy of data without interfering with writer operations, simplifying the coherency management.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If data is moved between cores using traditional load/store instructions, then data is transferred, but cache line ownership must be transferred and coherency state changes occur

Engineering Contradiction:
Improvedata transferVSAvoidtime for cache line ownership transfer
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent uses snapshot copies to transfer data between cores without transferring cache line ownership. Readers obtain a snapshot copy of the cache line data without requiring the cache line to be invalidated or transferred in the traditional sense, eliminating the time penalty associated with ownership transfer and coherency state changes.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The snapshot mechanism performs preliminary copying of cache line data before the actual read operation completes. This preliminary action creates a stable copy that can be accessed without subsequent coherency protocol interventions, reducing the overall time required for data transfer between cores.

Inventive Principle:
Principle #10Preliminary action

4Use of energy by moving object

If message passing architecture or software-managed memories are used to avoid coherency overhead, then energy consumption is reduced, but software complexity and development effort increase

Engineering Contradiction:
Improveenergy consumptionVSAvoidsoftware complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent implements hardware-supported snapshot and in-place write operations that automatically manage the complexity of snapshot creation and validation. Instead of requiring software to manually manage snapshot buffers and validation logic, the hardware provides atomic snapshot operations that self-manage the underlying complexity, reducing software burden while maintaining low energy consumption.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11816036B2Method and system for performing data movement operations with read snapshot and in place write update
Publication Date: 2023.11.14 INTEL CORP
  • US11816036B2 patent drawing
  • US11816036B2 patent drawing
  • US11816036B2 patent drawing

AI summary

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.