Read Verify for Residual Resistance in NAND Memory
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Solution Overview
Problem
In NAND memory structures, excessive residual resistance can occur due to trapped charge along the NAND string, leading to reduced performance and errors in data reading, which can overwhelm error correction capabilities, especially when residual resistance affects the conduction of NAND strings, causing them to register as non-conducting even when all select gates and memory cells are on.
Innovation Solution
A read verify operation is performed with all transistors of a NAND string turned on to determine if residual resistance exceeds a reference value, allowing for the downgrading of soft bit information for memory cells in NAND strings with excessive residual resistance, thereby improving data decoding accuracy using techniques like low-density parity check (LDPC) codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read operations are performed on NAND strings with trapped charge, then data can be read from memory cells, but residual resistance causes conduction errors and reduces reading accuracy
Solution Approach 1:
The patent performs a verify read operation before the actual data read operation. This preliminary action detects the presence of residual resistance by checking if the NAND string conducts when all select gates should be on. If residual resistance is detected, the system can then adjust soft bit information for subsequent reads, preventing erroneous data interpretation.
Solution Approach 2:
The patent implements a feedback mechanism where the result of the verify read operation influences the interpretation of the actual data read. The verify operation provides feedback about the conduction state of the NAND string, which is then used to adjust soft bit information and improve the reliability of error correction decoding.
2Reliability
If error correction codes are used to handle reading errors, then data integrity can be maintained, but excessive residual resistance errors can overwhelm error correction capabilities
Solution Approach 1:
The verify read operation serves as a preliminary action that identifies and flags NAND strings with excessive residual resistance before the actual data read. This allows the system to pre-adjust soft bit information, reducing the burden on error correction codes and preventing them from being overwhelmed by uncorrectable errors.
3Ease of operation
If all select gates are turned on during read operations, then memory cells can be accessed, but trapped charge in the channel creates residual resistance that prevents proper conduction
Solution Approach 1:
The verify read operation is performed as a preliminary action with all select gates turned on to detect residual resistance conditions. This allows the system to identify problematic NAND strings before actual data reading, enabling appropriate handling of the affected cells while maintaining normal operation of unaffected cells.
Data Source
AI summary
Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.