Self-adaptive Read Voltage Adjustment for Memory Error Rates

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Solution Overview

Problem

Conventional memory sub-systems face increased error rates and performance degradation due to time-varying error rates in non-volatile memories, as optimal read voltage levels become sub-optimal over time, leading to increased bit error rates and resource utilization for error recovery operations.

Innovation Solution

A self-adaptive read voltage adjustment scheme based on accumulated directional raw bit error rate (RBER) statistics, which identifies optimal read voltage levels by determining directional error rates for different write-to-read delay ranges and adjusts the read voltage levels dynamically to maintain reliability and performance targets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fixed read voltage levels are used in memory sub-systems, then initial read operations can be performed, but error rates increase over time as optimal voltage levels become sub-optimal due to time-varying error rates

Engineering Contradiction:
Improveerror rateVSAvoidadaptability to time-varying error rates
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic read voltage adjustment by continuously monitoring error rates and adapting the read voltage level accordingly. The system transitions from fixed voltage levels to dynamically adjustable voltage levels that respond to changing memory characteristics over time, thereby maintaining optimal read operations despite time-varying error rates.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where error rates from read operations are monitored and fed back to adjust the read voltage level. This closed-loop control system uses the observed error patterns to automatically tune the read voltage, ensuring that the memory sub-system maintains low error rates even as memory characteristics degrade or change over time.

Inventive Principle:
Principle #23Feedback

2Reliability

If read voltage levels are adjusted to maintain optimal performance, then error rates decrease, but system complexity increases due to additional monitoring and adjustment mechanisms

Engineering Contradiction:
Improveread operation reliabilityVSAvoidvoltage adjustment mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-service mechanism where the memory sub-system automatically monitors its own error rates and adjusts its read voltage levels without external intervention. The system uses its own operational data to self-tune, eliminating the need for complex external control mechanisms while maintaining optimal performance.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the operational parameters of the memory sub-system by dynamically adjusting the read voltage level based on observed error patterns. This parameter adaptation allows the system to maintain optimal performance across different memory states and aging conditions without requiring fundamentally new hardware architectures.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If dynamic read voltage adjustment is implemented, then throughput and latency improve, but power consumption increases due to continuous monitoring and adjustment operations

Engineering Contradiction:
Improvedata access throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic monitoring and adjustment of read voltage levels rather than continuous adjustment. By monitoring error rates at intervals and adjusting voltage levels periodically, the system maintains improved throughput and latency while reducing power consumption compared to continuous adjustment mechanisms.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11410743B2Self-adaptive read voltage adjustment using directional error statistics for memories with time-varying error rates
Publication Date: 2022.08.09 MICRON TECHNOLOGY INC
  • US11410743B2 patent drawing
  • US11410743B2 patent drawing
  • US11410743B2 patent drawing

AI summary

A processing device in a memory system determines a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times. The processing device further determines whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion, and responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusts a read voltage level associated with the first range.