Read Voltage Correction in Nonvolatile Semiconductor Storage
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Solution Overview
Problem
Nonvolatile semiconductor storage devices, such as NAND flash memory, face significant latency issues during read voltage correction due to fluctuations in threshold voltage distributions caused by data retention and read disturb, which necessitate complex error bit counting and processing.
Innovation Solution
A nonvolatile semiconductor storage device with a control circuit that stores known data with imbalanced binary logic in separate areas, allowing for the detection of error bits and calculation of their relative difference to adjust the read voltage based on comparison with predetermined values, thereby simplifying the correction process and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC decoding is performed on read data to detect uncorrectable errors, then data reliability is improved, but processing time increases significantly when errors are detected
Solution Approach 1:
The patent performs preliminary error detection using a parity check before attempting full ECC decoding. By checking the parity bit first, the system can identify obviously erroneous data and trigger voltage correction only when necessary, avoiding the time-consuming full ECC decoding process for correct data while maintaining data reliability through selective error handling
2Reliability
If read voltage correction processing is performed when ECC decoding fails, then data reliability is improved, but latency increases due to additional processing steps
Solution Approach 1:
The patent performs preliminary actions by storing known data with predetermined parity bits and performing parity checks before full ECC decoding. This allows the system to proactively identify when voltage correction is needed without waiting for complete ECC failure, reducing latency by preparing correction data in advance and triggering correction only when the parity check indicates errors
Solution Approach 2:
The system uses the stored known data with predetermined parity bits to self-diagnose read errors. By comparing the read parity bit with the predetermined parity bit, the system can automatically detect errors and trigger voltage correction without external intervention, improving both reliability and response time
3Measurement precision
If complex error bit counting and processing is performed to correct read voltage, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential error detection function by using parity bits separately from the main data. Instead of performing complex error bit counting on all data, the system extracts the parity bit for quick comparison with the predetermined parity bit, achieving accurate error detection with minimal processing complexity
Solution Approach 2:
The patent applies different processing qualities to different parts of the data. Known data areas use simple parity bit comparison for error detection, while only triggering full voltage correction processing when errors are detected. This localized approach maintains high measurement precision for error detection while reducing overall processing complexity by avoiding unnecessary complex operations on correct data
Data Source
AI summary
A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.