Read Voltage Offsets for Partially Programmed Memory Blocks
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Solution Overview
Problem
Existing memory devices experience high read latency due to frequent re-read operations on partially-programmed blocks, which are caused by incorrect read voltages resulting from floating gate-to-floating gate coupling issues, leading to increased ECC failures.
Innovation Solution
Proactively adjust read voltages on partially-programmed blocks based on a wordline-specific pattern of unsuccessful reads to reduce the re-read trigger rate, using a partially-programmed read logic to identify vulnerable wordlines and apply appropriate offset voltages before reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If standard read voltage is applied to partially-programmed blocks, then read operations can be performed, but read latency increases due to frequent re-read operations
Solution Approach 1:
The system proactively adjusts read voltages on partially-programmed blocks before performing read operations. The controller identifies when a block is partially programmed and pre-applies appropriate read voltage offsets to compensate for floating gate coupling effects, thereby preventing read failures and reducing re-read operations.
Solution Approach 2:
The system dynamically changes read voltage parameters based on the programming state of memory blocks. By detecting partial programming conditions, the controller modifies read voltage levels and offsets specifically for affected blocks, optimizing read operations and eliminating the need for repeated read attempts.
2Loss of time
If read voltage is adjusted to prevent re-read operations, then read latency is reduced, but device complexity increases
Solution Approach 1:
The controller implements a feedback mechanism that monitors the programming state of memory blocks. When partial programming is detected, the system feeds this information back to adjust read voltage settings, creating a closed-loop control system that automatically optimizes read operations without requiring complex external intervention.
Solution Approach 2:
The memory controller performs self-service by automatically detecting partially-programmed blocks and adjusting its own read voltage parameters. This self-regulating approach eliminates the need for additional external control logic or complex intervention mechanisms, keeping the system relatively simple while achieving improved read performance.
3Productivity
If proactive voltage adjustment is implemented, then re-read trigger rate decreases, but manufacturing complexity increases
Solution Approach 1:
The voltage adjustment mechanism serves multiple functions: it compensates for partial programming effects, prevents read failures, and extends device lifespan. This multi-functional approach consolidates several potential subsystems into a single integrated control mechanism, simplifying the overall manufacturing process despite the enhanced functionality.
Data Source
AI summary
Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.