Separate Read-Write Control Gates for Low-Disturb Memory Strings
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Solution Overview
Problem
Conventional memory devices face issues with read disturbance and structural degradation due to shared control gates for both read and write operations, leading to inferior performance and unreliable memory operations.
Innovation Solution
The implementation of separate read and write control gates associated with memory cell strings, allowing for distinct voltage control during read and write operations to prevent read disturbance and enhance program-erase window and current during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate read and write control gates are implemented, then read disturbance is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The control gate is segmented into separate read control gate and write control gate structures. Each control gate is independently formed with its own gate electrode and gate dielectric layer, allowing distinct voltage control during read and write operations. This segmentation eliminates the read disturbance issue by preventing unwanted charge injection into the charge storage structure during read operations, while maintaining reliable memory operations.
2Productivity
If separate read and write control gates are implemented, then program-erase window and read current are improved, but manufacturing complexity increases
Solution Approach 1:
The control gate structure is divided into separate read and write control gates formed in different trenches. The write control gate is formed in a first trench with write control gate dielectric and write control gate electrode, while the read control gate is formed in a second trench with read control gate dielectric and read control gate electrode. This segmentation enables optimized voltage control for each operation type, improving program-erase window and read current characteristics.
Solution Approach 2:
The separate read and write control gates are arranged in different spatial dimensions (different trenches at different locations). This dimensional separation allows independent control of read and write operations without interference, enabling improved program-erase window and read current while maintaining a compact vertical structure suitable for scaling.
3Reliability
If separate read and write control gates are implemented, then read disturbance is prevented, but device area increases
Solution Approach 1:
The control functionality is segmented into separate read and write control gates, each with its own gate electrode and dielectric layer formed in distinct trenches. This segmentation prevents read disturbance by isolating the read control gate from the charge storage structure during read operations, ensuring reliable read operations without unwanted charge injection.
Solution Approach 2:
The read control gate and write control gate structures are nested within the same memory cell vertical stack, with each control gate formed in its own trench around the charge storage structure. This nested arrangement allows separate control functionality while maintaining a compact footprint, as both control gates share the same vertical space rather than requiring lateral expansion.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.