Read/Write Switching Circuit With Signal Amplification for DRAM Speed
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Solution Overview
Problem
The data transmission speed of current DRAMs is limited, particularly due to the reduced driving capability of sense amplifiers (FSAs) as they become smaller, which affects the speed at which local data lines are pulled up or down during read/write operations.
Innovation Solution
A read/write switching circuit is introduced with an amplification module between data and complementary data lines to accelerate signal distinction, reducing the reliance on FSA driving capability, thereby enhancing data transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the sense amplifier size is reduced to meet device miniaturization requirements, then the area occupied by the sense amplifier is reduced, but the driving capability of the sense amplifier deteriorates, which slows down the data transmission speed
Solution Approach 1:
A read/write switching circuit is introduced as an intermediary component between the sense amplifier and the data lines. This switching circuit includes pull-up and pull-down transistors that actively drive the data lines during read operations, compensating for the reduced driving capability of miniaturized sense amplifiers and maintaining high data transmission speed
Solution Approach 2:
The driving function is segmented into two parts: the sense amplifier performs the primary sensing function, while the read/write switching circuit handles the driving function. This segmentation allows the sense amplifier to be miniaturized without sacrificing driving capability, as the switching circuit assumes the driving burden
2Area of moving object
If the sense amplifier size is reduced, then the area is reduced, but the ability to pull up or down local data lines during read/write operations deteriorates
Solution Approach 1:
The read/write switching circuit acts as an intermediary that receives control signals from the sense amplifier and directly controls the pull-up and pull-down operations on data lines through dedicated transistors, enabling effective data line driving despite the reduced size of the sense amplifier
Solution Approach 2:
The read/write switching circuit dynamically activates pull-up and pull-down transistors based on operation mode (read or write), providing adaptive driving capability that compensates for the static limitations of the miniaturized sense amplifier
Data Source
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AI summary
Some embodiments of the present application relate to the field of semiconductor technologies, and disclose a read/write switching circuit and a memory. The read/write switching circuit includes: a first data line connected to a bit line through a column select module, a first complementary data line connected to a complementary bit line through the column select module, a second data line and a second complementary data line, and further includes: a read/write switching module configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line and the second complementary data line during read and write operations in response to read and write control signals; and an amplification module connected between the first data line and the first complementary data line and configured to amplify data of the first data line and data of the first complementary data line.