Read and Write Window Budget for Two-Level Memory Systems
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Solution Overview
Problem
In two-level memory (2LM) systems, there is a challenge in balancing write/read completion times with acceptable error rates, particularly when using non-volatile memories like phase change memory, where reducing errors through error correction codes increases completion times.
Innovation Solution
Implementing a read and write window budget that differentiates between two sets of memory addresses in the second level memory, using a foreground write process with no error correction for quicker writes and a background write process with error correction and a multiple pulse-verification algorithm to narrow cell threshold voltage distributions, thereby reducing errors and optimizing completion times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to reduce error rates in non-volatile memory, then reliability is improved, but write completion time increases
Solution Approach 1:
The patent segments the write operation into two distinct processes: foreground write process that completes quickly without error correction, and background write process that performs error correction and pulse-verification algorithms. This segmentation allows the system to meet write completion time requirements while still performing error correction, thereby resolving the contradiction between reliability and write speed.
Solution Approach 2:
The patent performs preliminary error correction and pulse-verification operations in the background process before the data is permanently committed to the non-volatile memory. By preparing error correction codes and verifying data integrity in advance during the background process, the system ensures high reliability without delaying the foreground write completion.
2Loss of time
If foreground write process is used for faster writes, then write completion time is reduced, but error rate increases
Solution Approach 1:
The patent divides the write operation into foreground and background segments, where the foreground process handles time-critical writes without error correction to meet completion time requirements, while the background process handles error correction and verification to ensure data integrity. This segmentation resolves the contradiction by assigning different functions to different time periods.
Solution Approach 2:
The patent introduces a background write process as an intermediary that performs error correction and pulse-verification algorithms on data written by the foreground process. This intermediary background process ensures that even though the foreground write completes quickly without full error correction, the data eventually achieves high reliability through the background verification process.
3Manufacturing precision
If multiple pulse-verification algorithm is used to narrow cell threshold voltage distributions, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the complex pulse-verification algorithm into manageable steps executed during the background write process. By dividing the verification into discrete pulse applications and threshold checks performed asynchronously in the background, the system achieves precise control over cell threshold voltage distributions without overwhelming the foreground write operations.
Solution Approach 2:
The background write process performs self-service error correction and pulse-verification operations on previously written data without requiring external intervention or complicating the main write path. The system uses its own background resources to verify and correct errors, thereby achieving high manufacturing precision while keeping the primary write device simple and efficient.
Data Source
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AI summary
Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2LM) system. In some examples, a read and write window budget may be established for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. Other examples are described and claimed.