Readable Configuration Latch Circuit With Non-Terminated Bit Line
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Solution Overview
Problem
The semiconductor industry faces challenges in designing programmable logic devices like FPGAs due to difficulties in incorporating desired logic within specified die size, routing signals, and ensuring signal stability, particularly with the use of SRAM cells which are foundry and process dependent, and the inefficiency of registers as storage elements.
Innovation Solution
The implementation of a configuration memory latch circuit with a word line write signal, a word line read signal, a non-terminated bit line, transmission gates, a NAND gate, an inverter, a pull-down network, and a sensing block, allowing for area-efficient and readable storage elements, enabling the use of latches as storage elements in FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If SRAM cells are used as storage elements, then area efficiency is improved, but foundry and process dependency increases causing migration difficulties
Solution Approach 1:
The patent segments the storage function from the SRAM cell structure by using latches with non-terminated bit lines that can be independently configured. This allows the storage elements to be decoupled from foundry-specific SRAM implementations, enabling portability across different foundries and processes while maintaining area efficiency.
Solution Approach 2:
The patent changes the fundamental parameter of bit line termination from terminated (traditional SRAM) to non-terminated, which fundamentally alters the storage mechanism to be less dependent on specific foundry processes. This parameter change enables the same latch structure to function reliably across different foundries and process nodes.
2Ease of operation
If registers are used as storage elements, then readability and availability are improved, but area efficiency deteriorates
Solution Approach 1:
The patent merges the advantages of latches (area efficiency) with the advantages of registers (readability) by creating a latch structure with non-terminated bit lines that can be read. This combines the compactness of latch-based storage with the read capability traditionally associated with register-based storage, eliminating the need to choose between area efficiency and readability.
3Area of moving object
If latches are used as storage elements, then area efficiency is improved, but reading capability deteriorates due to difficulty in reading latch state
Solution Approach 1:
The patent introduces a sensing block as an intermediary component that facilitates reading the latch state. The sensing block detects the state of the non-terminated bit line and provides a readable output, acting as a mediator between the compact latch structure and the read operation. This intermediary enables area-efficient latch-based storage to maintain full read capability.
4Area of moving object
If higher levels of integration are implemented, then silicon space and cost are reduced, but design complexity and signal stability challenges increase
Solution Approach 1:
The patent creates a universal latch-based storage element that can be used across different contexts and configurations within the FPGA. The non-terminated bit line latch structure serves multiple functions including storage, reading, and configuration, reducing the need for separate specialized components and simplifying overall design while enabling higher integration.
Data Source
AI summary
An area efficient readable and resettable configuration memory latch maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.