Data Readout Circuit Biasing for Non-Volatile Memory Stability
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Solution Overview
Problem
Existing data readout circuits face issues with erroneous writing and incorrect data reading when high voltages are applied due to increased drain-source voltage in PMOS OTP elements, and an imbalance between latch current and OTP on current, especially when the power supply voltage is high.
Innovation Solution
A data readout circuit design incorporating bias circuits that supply predetermined bias voltages to MOS transistors, ensuring independent latch and OTP currents regardless of the power supply voltage, and using capacitors to stabilize voltages and prevent undershoots, thereby maintaining accurate data reading and preventing erroneous writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage is applied to the power supply terminal during data read-out operation, then the power supply capability is improved, but the drain-source voltage of the PMOS OTP element increases causing erroneous writing
Solution Approach 1:
A bias circuit is introduced as an intermediary component between the power supply terminal and the PMOS OTP element. This bias circuit generates a predetermined bias voltage that is lower than the power supply voltage, thereby mediating the voltage relationship and preventing the drain-source voltage from exceeding the write voltage threshold even when high voltage is applied to the power supply terminal.
Solution Approach 2:
The patent changes the voltage parameter at the gate of the PMOS transistor by introducing a bias circuit that outputs a predetermined bias voltage. This parameter change ensures that the drain-source voltage remains below the write voltage threshold, preventing erroneous writing while allowing high power supply voltage to maintain reading capability.
2Power
If high voltage is applied to the power supply terminal during data read-out operation, then the power supply capability is improved, but the latch current becomes larger than the OTP on current causing incorrect data reading
Solution Approach 1:
The bias circuit acts as an intermediary that decouples the latch current from the power supply voltage. By generating a predetermined bias voltage independent of the power supply voltage, the bias circuit ensures that the latch current remains balanced with the OTP on current even when high voltage is applied, preventing incorrect data reading.
Solution Approach 2:
The patent changes the voltage parameter at the gate of the PMOS transistor in the latch circuit by introducing a bias circuit that outputs a predetermined bias voltage. This parameter change ensures that the latch current does not increase excessively with power supply voltage, maintaining proper current balance and data reading accuracy.
3Measurement precision
If the drain-source voltage of the PMOS OTP element is increased to improve reading capability, then the reading sensitivity is improved, but the risk of erroneous writing increases
Solution Approach 1:
The bias circuit serves as an intermediary that controls the gate voltage of the PMOS transistor. By generating a predetermined bias voltage that is lower than the power supply voltage, the bias circuit mediates the relationship between reading capability and write protection, allowing sufficient drain-source voltage for reading while preventing erroneous writing.
Data Source
AI summary
Provided is a data readout circuit capable of, even when a high voltage is applied during data read-out operation, preventing erroneous writing of the data and reading out the data correctly. The data readout circuit includes: a non-volatile storage element; a latch circuit including: an input inverter; an output inverter; and a MOS transistor; a first MOS transistor connected between the non-volatile storage element and the latch circuit; a second MOS transistor connected between the latch circuit and the first power supply terminal; a first bias circuit configured to bias a gate of the first MOS transistor; and a second bias circuit configured to bias the MOS transistor in the latch circuit, each of the first bias circuit and the second bias circuit being configured to output a predetermined bias voltage when the data in the non-volatile storage element is read out.