Readout Circuit Structure for DRAM Bit Line Precharge
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Solution Overview
Problem
Current DRAMs face performance limitations due to insufficient charging speed of bit lines and complementary bit lines, exacerbated by the reduction in transistor sizes, which affects read-write performance.
Innovation Solution
A readout circuit structure is introduced, comprising first and second sense amplification circuits and equalization pipes, where the equalization pipes directly precharge bit lines and complementary bit lines to a preset voltage, bypassing the need for a switching transistor during precharge, thereby enhancing charging speed and reducing layout area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching transistors are used to precharge bit lines, then the precharge function can be achieved, but the charging speed is insufficient and layout area is increased
Solution Approach 1:
The patent extracts the precharge function from the switching transistor and implements it through dedicated equalization pipes. The equalization pipes are separately configured to precharge bit lines and complementary bit lines, separating the precharge function from the switching function, thereby achieving faster charging speed without increasing the layout area of the readout circuit.
Solution Approach 2:
The equalization pipes serve multiple functions: they precharge bit lines, precharge complementary bit lines, and can be integrated into the readout circuit structure. This multi-functionality allows the same structural elements to perform both precharge and switching operations, eliminating the need for additional switching transistors and reducing layout area.
2Area of moving object
If transistor sizes are reduced, then device integration is improved, but charging speed of bit lines deteriorates
Solution Approach 1:
The patent segments the precharge function into dedicated equalization pipes that are separately configured for bit lines and complementary bit lines. This segmentation allows the precharge operation to be performed by specialized structures rather than relying on the scaling transistors, thus maintaining fast charging speed even as transistor sizes are reduced for better integration.
3Reliability
If equalization pipes are disposed on both sides of sense amplification circuits, then precharge coverage is improved, but layout area increases
Solution Approach 1:
The patent merges the equalization pipes with the sense amplification circuit structure by disposing them adjacent to the circuits rather than on both sides. This merging approach achieves sufficient precharge coverage for reliable operation while reducing the layout area compared to the conventional approach of placing equalization pipes on both sides of each sense amplification circuit.
Data Source
AI summary
A readout circuit structure is provided, which includes: a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, here the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a first bit line, and is coupled to the other memory array by a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a second bit line, and is coupled to the other memory array by a second complementary bit line; a first equalization pipe, connected to the first bit line; a second equalization pipe, connected to the first complementary bit line; a third equalization pipe, connected to the second bit line; and a fourth equalization pipe, connected to the second complementary bit line.