DRAM Readout Circuit Layout for Offset Cancellation
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Solution Overview
Problem
Current DRAM performance is limited by the long time required for the sense amplification module to process data due to the offset cancellation process, leading to increased power consumption and reduced data processing speed.
Innovation Solution
A readout circuit layout structure with first and second readout circuit structures arranged adjacent to each other, featuring isolation modules, sense amplification modules, and offset cancellation modules, where data is transmitted to the bit line connected to the sense amplification module in advance to reduce processing time, and the circuit layout is optimized for minimized area and shortest connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sense amplification module performs offset cancellation process before data processing, then the accuracy of data reading is improved, but the time required for data processing increases
Solution Approach 1:
The patent performs offset cancellation in advance during the precharge phase before actual data reading operations. The readout circuit includes offset cancellation modules that eliminate offset voltages beforehand, so that when data reading occurs, the amplification process can proceed without delay for offset correction, thus resolving the contradiction between accuracy and processing time.
2Productivity
If the sense amplification module processes data sequentially, then the circuit structure is simplified, but the data processing speed decreases
Solution Approach 1:
The patent divides the readout circuit into multiple independent readout circuits, each capable of processing data from different memory banks simultaneously. This segmentation allows parallel processing of multiple data streams, significantly increasing data processing speed while maintaining relatively simple individual circuit structures.
Solution Approach 2:
The patent combines multiple readout circuits and memory banks into an integrated system where they operate in parallel. By merging multiple processing units into a unified architecture, the system achieves high-speed data processing through parallelism without requiring excessively complex individual circuit designs.
3Reliability
If the readout circuit is designed with complete isolation modules for each memory bank, then the reliability of data reading is improved, but the area occupied by the circuit increases
Solution Approach 1:
The patent designs isolation modules that serve multiple memory banks simultaneously rather than dedicating separate isolation modules to each bank. These universal isolation modules can be configured to isolate different combinations of memory banks, providing the necessary reliability while reducing the total circuit area by eliminating redundancy.
Data Source
AI summary
The present disclosure relates to the field of semiconductor circuit design, and in particular to a readout circuit layout structure and a method of reading data. The readout circuit layout structure includes: a first readout circuit structure and a second readout circuit structure having identical structures, wherein the first readout circuit structure and the second readout circuit structure each include: a first isolation module, configured to be turned on according to a first isolation signal, electrically connect a bit line and a first readout bit line, and electrically connect a complementary bit line and a first complementary readout bit line; a second isolation module, configured to be turned on according to a second isolation signal, electrically connect the first readout bit line and a second readout bit line, and electrically connect the first complementary readout bit line and a second complementary readout bit line.