Readout Circuit for Non-Volatile Memory with Shared Bias Control
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Solution Overview
Problem
Conventional floating gate tunnel oxide non-volatile memory devices experience reduced readout margin for distinguishing between 0 and 1 due to deterioration in film quality, making it difficult to differentiate data across various operating temperatures and power supply voltages.
Innovation Solution
A readout circuit configuration that includes a memory element, a select gate transistor, NMOS and PMOS transistors, and a bias circuit, where the gates of the memory element and NMOS transistor are controlled by the same voltage, reducing characteristics fluctuations and eliminating the need for a voltage comparator circuit, thereby enhancing the readout margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated rewriting is performed in conventional FLOTOX non-volatile memory, then data storage capability is maintained, but film quality of tunnel oxide deteriorates causing threshold difference to decrease
Solution Approach 1:
The patent changes the readout mechanism from voltage-based comparison to current-based comparison. By measuring current characteristics directly from the memory element during readout, the system maintains reliability across repeated rewriting cycles without being affected by deteriorating tunnel oxide film quality that reduces threshold voltage differences.
2Duration of action of moving object
If threshold difference becomes smaller due to film deterioration, then repeated rewriting is achieved, but readout margin for distinguishing 0 and 1 is reduced
Solution Approach 1:
The patent replaces the voltage comparator circuit with a current-based readout mechanism. Instead of comparing voltages that become indistinguishable due to film deterioration, the system directly measures and compares current characteristics, which remain sufficiently differentiated even after repeated rewriting cycles.
3Ease of operation
If voltage comparator circuit is used to distinguish data, then data reading is achieved, but circuit complexity increases and readout margin is insufficient
Solution Approach 1:
The patent extracts and removes the voltage comparator circuit from the readout system. By eliminating this complex component and replacing it with a simpler current-based measurement approach, the system achieves data reading capability with reduced circuit complexity and improved readout margin.
4Ease of operation
If conventional readout circuit configuration is used, then data reading is possible, but circuit area is large and costs are high
Solution Approach 1:
The patent merges the readout function with the existing memory cell structure by using current-based measurement that integrates with the memory element's natural current characteristics. This eliminates the need for separate complex comparator circuits, thereby reducing overall circuit area and manufacturing costs while maintaining data reading functionality.
Data Source
AI summary
Provided is a readout circuit for a non-volatile memory device, which has a large readout margin for distinguishing between 0 and 1 of data and has a small circuit area. A voltage output from a single bias circuit is applied to a gate of a memory element and a gate of an NMOS transistor serving as a reference current source to be compared with a current flowing through the memory element. Thus, the gates are controlled by the same voltage, and hence characteristics fluctuations in the operating temperature range and the operating power supply voltage range are reduced. Therefore, a large readout margin for distinguishing 0 and 1 of data can be obtained, resulting in a simplified circuit configuration.