Real-Time External Compensation Driving Circuit for Electroluminescent Displays
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Solution Overview
Problem
Existing driving circuits for electroluminescent displays face challenges in generating a desired sensing gate signal within the limited time constraints of the vertical blanking interval, particularly as the vertical resolution of the display panel increases, leading to insufficient time for all stages of the gate driver to operate effectively.
Innovation Solution
A driving circuit that performs sensing drive operations during the vertical active period, utilizing a timing controller to generate gate shift clocks and selection signals, and a gate driver with stages that shift the gate start pulse to generate output signals, allowing for a desired sensing gate signal to be produced without time constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sensing drive operation is performed in the vertical blanking interval, then the display drive operation can be completed, but the time available for sensing drive is insufficient as vertical resolution increases
Solution Approach 1:
The patent dynamically switches between display drive mode and sensing drive mode during the vertical active period. The gate driver can change its operation mode based on timing signals, allowing flexible allocation of time resources. This dynamic switching enables sufficient time for sensing operations even with high vertical resolution displays.
Solution Approach 2:
The patent performs sensing drive operations continuously during the vertical active period by utilizing periods when the display drive is not actively updating pixels. By overlapping sensing operations with display operations in time, the system maintains continuous useful action without extending the overall frame time, thus solving the time constraint problem.
2Reliability
If all stages of the gate driver operate sequentially, then the gate signal can be generated, but the operation time exceeds the vertical blanking interval duration
Solution Approach 1:
The patent performs preliminary sensing operations during the vertical active period before the vertical blanking interval ends. By completing the sensing drive operation in advance during the active period, the system ensures that all gate driver stages have sufficient time to operate sequentially and reliably without being constrained by the short vertical blanking interval.
Solution Approach 2:
The patent moves the sensing drive operation from the time dimension of the vertical blanking interval to the time dimension of the vertical active period. This dimensional shift in timing allows the gate driver stages to operate at their natural sequential speed without artificial time pressure, maintaining reliability while improving effective productivity.
3Measurement precision
If sensing drive operation is performed separately from display drive operation, then each operation can be optimized, but the overall time required increases
Solution Approach 1:
The patent merges the sensing drive operation and display drive operation into a unified timing framework during the vertical active period. By combining these operations and allowing them to share the same time resource, the system achieves both sensing accuracy and display performance without requiring separate time allocations, thus reducing the total duration.
Solution Approach 2:
The gate driver is designed with multi-functionality to perform both display drive and sensing drive operations using the same hardware resources during the vertical active period. This universal design allows the system to achieve both sensing accuracy and display performance simultaneously, eliminating the need for separate operation periods and reducing overall time requirements.
Data Source
AI summary
A driving circuit for real-time external compensation and an electroluminescent display including the same are disclosed. The driving circuit includes a timing controller generating a gate shift clock group, a gate start pulse, and first and second selection signals and a gate driver generating a gate signal based on the control of the timing controller and supplying the gate signal to a display panel. The gate driver includes a plurality of stages which shifts the gate start pulse in accordance with the gate shift clock group to generate an output signal and supplies the output signal to a first output node, a first output control switch connected between a second output node connected to a gate line of the display panel and the first output node, and a second output control switch connected between the second output node and an input terminal of a gate low voltage.