Real-Time Constraint Verification in Electronic Design Automation
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Solution Overview
Problem
Conventional electronic design processes are inefficient due to the lack of real-time constraint verification, leading to costly and time-consuming iterative processes, especially in complex sub-micron integrated circuits, where physical design tools and schematic design tools are unaware of electrical parasitics and design rule violations until the layout is complete.
Innovation Solution
A method and system that bridge the schematic and physical design environments, using connectivity information to identify and verify complex design rule violations interactively and in real-time during the placement or routing stages, employing scratch pads for temporary data storage and ACID database transactions to provide immediate feedback on design rule compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sequential verification is performed after layout completion, then design rule violations can be identified, but the design process becomes iterative and time-consuming
Solution Approach 1:
The patent performs design rule checking and constraint verification during the physical design stage (placement and routing) rather than waiting until layout completion. This preliminary verification identifies violations early, preventing iterative revisions and reducing overall design time while maintaining detection accuracy
2Productivity
If physical design tools operate independently of schematic design tools, then tool complexity is reduced, but connectivity information and design rule violations cannot be verified in real-time
Solution Approach 1:
The patent integrates schematic design environment and physical design environment through a unified database system. Connectivity information from schematic tools is merged with physical layout data, enabling real-time constraint verification while maintaining tool independence through standardized data interfaces
3Reliability
If iterative design revisions are performed to resolve violations, then design quality improves, but resource wastage increases
Solution Approach 1:
The patent implements continuous feedback mechanisms during the physical design process by monitoring constraint satisfaction in real-time. When violations are detected, immediate feedback guides design modifications, eliminating the need for multiple iterative cycles and reducing computational resource wastage while maintaining design quality
Data Source
AI summary
Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.