Real-Time Design Checking for Integrated Circuit Layouts

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Solution Overview

Problem

Conventional optical lithography technologies face challenges in accurately projecting sub-wavelength feature geometries due to limitations in light wavelength and lens systems, leading to potential design errors and failures in semiconductor integrated circuit fabrication.

Innovation Solution

A design tool is configured to perform real-time automated design checking by comparing entered design elements against a database of known compliant and non-compliant patterns, alerting designers to violations and providing corrections, such as substituting valid design elements or suggesting layout adjustments, to prevent errors before fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional optical lithography is used to project smaller feature geometries, then integration density increases, but manufacturing precision deteriorates due to resolution limits

Engineering Contradiction:
Improveintegration densityVSAvoidfeature geometry accuracy
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The system performs preliminary design rule checking and validation before photolithography fabrication. By comparing design patterns against a database of known good and bad patterns, the system identifies and corrects potential manufacturing errors in advance, preventing precision loss during the actual lithography process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A computational design verification system acts as an intermediary between the design stage and photolithography fabrication. This intermediary layer analyzes design patterns, compares them against established rules and known problematic patterns, and provides corrections before the design reaches the lithography process, thereby maintaining manufacturing precision

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If design checking is performed after fabrication, then manufacturing flexibility is maintained, but reliability deteriorates due to costly rework

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoiddesign correctness
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Design rule checking and validation are performed before photolithography fabrication rather than after. By validating designs in advance against comprehensive design rules and known problematic patterns, the system ensures design correctness upfront, preventing costly rework while maintaining manufacturing flexibility

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system provides immediate feedback to designers when design rule violations or problematic patterns are detected. This real-time feedback mechanism allows designers to correct issues before fabrication, improving reliability without restricting manufacturing flexibility

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8807948B2System and method for automated real-time design checking
Publication Date: 2014.08.19 CADENCE DESIGN SYST INC
  • US8807948B2 patent drawing
  • US8807948B2 patent drawing
  • US8807948B2 patent drawing

AI summary

Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.