Real-Time Memory Tester for NAND Voltage Monitoring

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Solution Overview

Problem

Conventional NAND testing and debugging methods are limited in their ability to efficiently monitor and manage internal voltages and operations in real-time, leading to suboptimal performance and reliability in managed NAND memory systems.

Innovation Solution

A memory tester with an integrated test flow controller and real-time analyzer that simultaneously uses both managed NAND and NAND interfaces to monitor internal voltages and operations, enabling advanced testing and debugging by processing data in real-time and controlling test flows based on monitored status signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional NAND testing methods are used, then device complexity is reduced, but measurement precision and real-time monitoring capability deteriorate

Engineering Contradiction:
Improvereal-time monitoring capabilityVSAvoidtester structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the test flow controller and real-time analyzer into an integrated tester system that simultaneously manages both managed NAND and raw NAND interfaces. This combination enables precise real-time monitoring of internal voltages and operations while maintaining coordinated control through a unified architecture, resolving the contradiction between measurement precision and device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The tester is designed with multi-functionality to handle both managed NAND interface (for controller communication) and raw NAND interface (for direct device access). This universal capability allows the same device to perform diverse functions including voltage monitoring, operation tracking, and real-time analysis without requiring separate specialized equipment, thereby improving measurement precision without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If real-time monitoring of internal voltages and operations is implemented, then reliability and error detection are improved, but use of energy and device complexity increase

Engineering Contradiction:
Improveerror detection capabilityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The real-time analyzer continuously monitors internal voltages and operations without interruption, enabling persistent error detection and reliability improvement. This continuous monitoring action ensures that any anomalies are captured immediately, enhancing the system's ability to detect and respond to errors while maintaining optimal energy utilization through sustained operational awareness.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If advanced testing features like wear-leveling and peak current analysis are added, then productivity and reliability are improved, but device complexity increases

Engineering Contradiction:
Improvetesting efficiencyVSAvoidanalyzer functionality
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The analyzer is segmented into specialized functional modules, each dedicated to specific analysis tasks such as wear-leveling monitoring and peak current analysis. This segmentation allows the complex testing functionality to be organized into manageable, independent units that can operate efficiently in parallel, improving overall testing productivity while keeping each module's complexity可控.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11763908B2Memory system tester using test pad real time monitoring
Publication Date: 2023.09.19 MICRON TECHNOLOGY INC
  • US11763908B2 patent drawing
  • US11763908B2 patent drawing
  • US11763908B2 patent drawing

AI summary

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.