Real-Time Repair Analyzer for Memory Device Testing
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Solution Overview
Problem
Conventional memory device testing systems face challenges in capturing and processing failure data in real time, leading to inefficiencies in identifying and repairing defective memory cells, particularly in high-capacity devices like NAND Flash memory, due to the need for expensive high-speed storage and lengthy data processing times.
Innovation Solution
A memory device testing system that includes a signal generator, comparator, and real-time repair analyzer, which captures and analyzes failure data as it is read from the memory device, enabling immediate determination of repair solutions by generating address signals and using redundant blocks or columns to replace defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-capacity memory devices are tested using conventional ECR techniques, then the storage capacity of the ECR must be commensurate with the storage capacity of the memory device being tested, but this requires expensive high-speed SRAM devices
Solution Approach 1:
The patent uses a small-capacity ECR that captures only fail data addresses rather than storing all test data. This approach replaces the need for expensive high-capacity high-speed SRAM with a cheaper small-capacity ECR, achieving the same functional goal of identifying defective cells without the high cost of large high-speed memory
Solution Approach 2:
The patent extracts only the essential information (fail data addresses) from the test process and stores only this extracted data in the ECR. By separating the fail data capture function from the complete test data storage function, the system avoids the need for expensive high-capacity high-speed SRAM while maintaining effective defect identification
2Quantity of substance
If fail data is captured using conventional ECR techniques, then the ECR must store all test data, but this increases the complexity of the testing system
Solution Approach 1:
The patent extracts only the fail data addresses from the complete test data and stores only this extracted information in the ECR. This selective extraction reduces the data volume in ECR from gigabytes to much smaller sizes, thereby reducing ECR capacity requirements and overall system complexity
Solution Approach 2:
Instead of storing all test data and then identifying failures, the patent inverts the approach by using logic that generates only fail data addresses directly. This inversion transforms the data flow from storing comprehensive test data to generating only the necessary failure information, simplifying the system architecture
3Quantity of substance
If conventional testing methods are used to test high-capacity memory devices, then the tester must perform a significant number of cell accesses, but this increases the testing time
Solution Approach 1:
The patent replaces the mechanical sequential testing approach with a parallel processing system using multiple banks. Instead of testing cells sequentially in a single bank, the system divides the memory into multiple banks that can be tested simultaneously, reducing the total testing time while maintaining comprehensive coverage of all cells
4Ease of manufacture
If interleaved banks of DRAM are used to capture fail data, then the cost is reduced compared to high-speed SRAM, but additional complications arise in reconstructing the fail data
Solution Approach 1:
The patent extracts only the essential fail data addresses and stores them directly in the ECR with minimal processing. By extracting only the critical information needed for defect identification and storing it in a simplified format, the system avoids the complex reconstruction processes that would be required if complete test data were stored in interleaved DRAM banks
Data Source
AI summary
A memory device test system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device. Each item of read data is compared to the corresponding item of write data, and fail data is produced indicative of the results of the comparison. The fail data is applied to a real time repair analyzer, which also receives an address of the read data being read to generate each item of fail data. The addresses are captured responsive to respective fail data signals to provide a record of the block, column and bit of each word of data read from a defective memory cell. The addresses are accumulated while the data are read from the memory device during testing so that a repair solution is available virtually as soon as the test has been completed.