Stacked Semiconductor Package Rear-Side Power Feed for Lower Voltage Drop
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Solution Overview
Problem
Existing semiconductor packages face challenges in reducing voltage drop, shortening switching time, and minimizing occupied area due to congestion in circuit structures caused by power wiring on the front surfaces of semiconductor chips.
Innovation Solution
The semiconductor package design includes a first and second semiconductor chip stacked in a perpendicular direction, with power received through the rear surfaces of each chip, reducing congestion between circuit layers and utilizing through vias and redistribution structures for efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power wiring is placed on the front surface of semiconductor chips, then power delivery is achieved, but circuit congestion increases causing voltage drop and longer switching time
Solution Approach 1:
The patent moves power wiring from the front surface (2D plane) to the rear surface of the semiconductor chip, utilizing the third dimension (depth/thickness) to resolve circuit congestion. Through-holes penetrating the substrate enable power delivery without occupying front surface area, thus reducing voltage drop and switching time while eliminating circuit congestion.
Solution Approach 2:
The patent divides the power delivery path into multiple segments: rear surface wiring, through-holes penetrating the substrate, and front surface connections. This segmentation allows power to be delivered through different spatial zones, avoiding congestion in any single area while maintaining efficient power distribution.
2Area of stationary object
If semiconductor chips are stacked in perpendicular direction, then occupied area is minimized, but power delivery complexity increases
Solution Approach 1:
The through-holes in the substrate serve multiple functions: they provide mechanical support for stacking, enable power delivery through the substrate thickness, and facilitate thermal management. This multi-functionality simplifies the overall power delivery structure while maintaining compact stacking configuration.
3Reliability
If through vias are used for power penetration, then voltage drop is reduced, but manufacturing complexity increases
Solution Approach 1:
The through-holes are formed and prepared in the substrate before chip stacking and wire bonding operations. This preliminary preparation simplifies subsequent manufacturing steps by providing pre-established pathways for power delivery, reducing the overall manufacturing complexity despite the added through-hole formation step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces voltage drop, shortens switching time, and minimizes occupied area by optimizing power delivery and reducing circuit congestion, while allowing for efficient stacking and packaging of semiconductor chips.
Implementation Method 1
a first through via for power penetrating through the first substrate layer and electrically connecting the first circuit wiring structure and the first wiring structure with each other
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.