Intelligent Receive Buffer Management for Idle State Residency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional power management systems in computing platforms often allocate insufficient buffer space for idle durations, leading to premature exit from low power states and reduced energy efficiency, and rely on worst-case line speed for latency tolerance, limiting the use of deeper idle states.

Innovation Solution

A buffer management architecture that dynamically allocates buffer space based on observed bandwidth and latency tolerance, allowing for deeper idle states by partitioning buffer space between idle duration and resume duration, and includes a power management unit to determine and communicate buffer-related settings to IO devices, ensuring sufficient buffer space for both latency tolerance and idle duration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If buffer space is allocated based on worst-case line speed, then latency tolerance is ensured, but idle state depth is limited or buffer space must be increased

Engineering Contradiction:
Improvelatency toleranceVSAvoididle state depth
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies dynamics by transitioning from static worst-case buffer allocation to dynamic bandwidth-based allocation. The system continuously monitors actual bandwidth and adjusts buffer space allocation accordingly, allowing the buffer to adapt to real-time conditions rather than being fixed based on maximum theoretical speeds. This enables deeper idle states when actual bandwidth is lower than worst-case scenarios.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter used for buffer allocation from fixed worst-case line speed to observed actual bandwidth. By using measured bandwidth values that reflect real network conditions rather than theoretical maximums, the system can allocate sufficient buffer space for deeper idle states while still maintaining acceptable latency tolerance based on actual performance characteristics.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If insufficient buffer space is allocated to idle duration, then buffer space is optimized for resume duration, but platform exits idle state prematurely reducing energy efficiency

Engineering Contradiction:
Improvebuffer space allocationVSAvoidenergy efficiency
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent implements feedback mechanisms where the system monitors actual buffer usage patterns and bandwidth conditions during idle states. This feedback information is used to dynamically adjust buffer space allocation between idle duration and resume duration, ensuring that sufficient space is allocated to maintain idle state residency while still providing enough buffer for quick resumption when needed.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts buffer space allocation based on observed bandwidth conditions and actual usage patterns. When bandwidth is lower than worst-case scenarios, the system allocates more buffer space to idle duration, enabling deeper idle states and improved energy efficiency. When bandwidth conditions indicate higher demand, the system reallocates buffer space to maintain resume capability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9223379B2Intelligent receive buffer management to optimize idle state residency
Publication Date: 2015.12.29 INTEL CORP
  • US9223379B2 patent drawing
  • US9223379B2 patent drawing
  • US9223379B2 patent drawing

AI summary

Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.