Receive Clock Phase Alignment for High-Resolution Signal Reception
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Solution Overview
Problem
In real-time networks, asynchronous clock frequencies between sending and receiving participants limit signal resolution, and existing synchronization methods face challenges in achieving high resolution and scalability due to oscillator demands and cascading negative effects like jitter.
Innovation Solution
A flexible method is introduced where the reception clock of the receiving participant is derived from the counter clock, with its phase position adapted to match the signal clock, using a phase-locked loop to ensure value-synchronous representation of local time, allowing for higher sampling rates and reduced quantization errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the second clock frequency is increased to improve signal sampling resolution, then the resolution improves, but the oscillator demands and system complexity increase significantly
Solution Approach 1:
The patent introduces a time stamp counter as an intermediary component that operates at the lower second clock frequency but records time information with reference to the higher first clock frequency. This mediator allows the system to achieve high-resolution time measurement without requiring the entire system to operate at the higher frequency, thus reducing oscillator demands while maintaining measurement precision.
Solution Approach 2:
The patent transitions from a single-dimension approach (direct sampling at high frequency) to a multi-dimensional approach by introducing a second time domain with the time stamp counter. The receive counter maps both the first local time (at first clock frequency) and the second local time (at second clock frequency), enabling high-resolution measurement through coordinate transformation between different time domains rather than relying solely on high-frequency oscillation.
2Measurement precision
If master clock synchronization is implemented to achieve high resolution, then the resolution improves, but the system scalability is limited to around 10 devices due to cascading negative effects
Solution Approach 1:
The patent segments the time synchronization function by introducing a global time reference that is independently maintained by each participant through time stamp counters. Instead of a hierarchical master-slave structure where synchronization errors cascade, each device operates autonomously with its own time stamp counter that references the global time, allowing independent time measurement without cascading negative effects and enabling system scalability beyond 10 devices.
3Measurement precision
If a receive counter mapped to the first local time is added to achieve higher resolution, then the resolution improves, but the device complexity increases
Solution Approach 1:
The time stamp counter serves multiple functions: it records time information at the higher first clock frequency resolution, provides a reference for mapping between different time domains, and enables both high-resolution signal reception and autonomous timekeeping. This multi-functional design achieves high measurement precision without proportionally increasing device complexity, as the same counter structure supports multiple operational modes and purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal resolution and synchronization, reducing quantization errors and allowing for higher bit rates, while maintaining synchronization across multiple participants without significant oscillator demands.
Implementation Method 1
using a phase-locked loop to ensure value-synchronous representation of local time
Data Source
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AI summary
To specify a flexible method for receiving a signal (S) by a participant (12) of a real-time network (1), wherein the signal (S) has a signal clock (ZT11) with a signal clock frequency (f11) and the participant (12) includes a counter (Z2) which has a counter clock (ZT2) with a counter clock frequency (f2) and represents a local time (t2) of the participant (12), a receive clock (ZT20) of a receive counter (Z20) of the participant (12) is provided for sampling the signal (S), wherein the receive clock (ZT20) is derived from the counter clock (ZT2), whereby the receive counter (Z20) represents the local time (t2) of the participant (12). The phase of the receive clock (ZT20) is adapted to the phase of the signal clock (ZT11) when derived from the counter clock (ZT2) and the signal (S) is sampled with a receive clock frequency (f20) of the receive counter (Z20).