Receive Timing Manager Self-Calibration Without PLLs
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Solution Overview
Problem
Existing digital circuit designs for data reception are limited by round trip latency time, leading to restricted system speed, and the use of phase-locked loops (PLLs) complicates the design with analog components and additional buffering requirements, while non-PLL designs struggle with setup and hold time variations due to process, temperature, and voltage variations.
Innovation Solution
A novel receive timing manager (RTM) that self-calibrates the receive timing window across voltage and temperature variations, using edge detection logic and a multiplexer to select optimal sample points, allowing for smaller or larger sample windows based on data transfer speed, thereby eliminating the need for PLLs and reducing design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a non-PLL based design is used to capture data with an internal clock, then the design simplicity is improved, but the system speed is limited by the round trip latency time
Solution Approach 1:
The patent implements a dynamic timing adjustment mechanism where the sampling clock phase is continuously adjusted based on detected data transition points. The system dynamically selects optimal sampling points from multiple possible clock phases, allowing the design to adapt to varying latency conditions while maintaining simplicity without PLLs.
Solution Approach 2:
The system changes the sampling parameter (clock phase) based on detected transition points. By measuring actual latency and adjusting the sampling clock phase accordingly, the system optimizes data capture timing without requiring complex PLL circuitry, thus improving speed while keeping the design simple.
2Speed
If a PLL based design is used to extract clock from data, then the round trip latency issues are solved, but the device complexity increases due to analog circuit customization and FIFO requirements
Solution Approach 1:
The patent extracts only the essential function of clock synchronization from the complex PLL system. Instead of using a full PLL with analog circuits and FIFOs, the system extracts timing information directly from data transition points and uses simple digital logic to adjust sampling phases, achieving the same speed improvement without the complexity.
Solution Approach 2:
The patent replaces the mechanical/analog PLL system with a digital solution. Instead of using analog phase-locked loop circuits and FIFO buffers, the system uses digital detection of transition points and digital adjustment of sampling clock phases, simplifying the hardware while maintaining high data receiving speed.
3Speed
If the sampling point is positioned close to data transition points to maximize speed, then the data-receiving speed is improved, but setup and hold time requirements are violated causing sampling errors
Solution Approach 1:
The system performs preliminary detection of data transition points before actual data sampling. By first identifying where transitions occur and then positioning sampling points at optimal distances from these transitions, the system ensures reliable sampling while maximizing speed. This preliminary timing adjustment prevents setup and hold time violations.
Data Source
AI summary
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.