Receiver ADC Activation Modes for Lower-Power Signal Conversion
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Solution Overview
Problem
Semiconductor devices face challenges in optimizing performance while managing power consumption, particularly in receivers equipped with multiple analog-to-digital converters (ADCs), as all ADCs operating simultaneously lead to increased power consumption without considering signal types and frequencies.
Innovation Solution
The semiconductor device controls the activation of ADCs based on operating modes, adjusting the number and phase synchronization of ADCs according to signal types (NRZ or multilevel) and frequencies, using different phase detectors and equalizers to manage power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all ADCs are activated simultaneously to improve signal conversion performance, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic activation of ADCs based on signal characteristics. The receiver selectively activates a first number of ADCs for NRZ signals and a second number of ADCs for multilevel signals, allowing the system to adapt its conversion precision dynamically according to the actual signal type, thereby achieving optimal balance between accuracy and power consumption
Solution Approach 2:
The patent changes the operational parameters of the ADCs by adjusting the number of active converters based on signal frequency and type. By modifying this key parameter dynamically, the system achieves different levels of conversion precision matched to different operating conditions, resolving the contradiction between maintaining high accuracy and reducing power consumption
2Productivity
If multiple ADCs are activated to improve conversion performance, then signal processing capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the ADC functionality into multiple independent converters that can be selectively activated. By dividing the overall conversion task among multiple ADCs and activating only the necessary number based on signal requirements, the system improves processing capability while managing complexity through modular, selective operation
Solution Approach 2:
The patent creates a universal receiver architecture where the same physical ADCs can serve different signal types (NRZ and multilevel) by dynamically adjusting which ADCs are active. This multi-functional approach allows the system to handle various signal formats with a single configurable structure, improving versatility without proportionally increasing complexity
3Adaptability or versatility
If all ADCs operate at full capacity to maintain performance across different signal types, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic adaptation by detecting signal type and frequency, then adjusting the number of active ADCs accordingly. This dynamic configuration allows the receiver to adapt to different signal formats (NRZ or multilevel) while consuming only the necessary power for each specific operating condition
Solution Approach 2:
The patent changes operational parameters based on detected signal characteristics. By modifying the number of active ADCs as a key parameter in response to different signal types and frequencies, the system achieves versatile adaptability while optimizing power consumption for each specific operating mode
Data Source
AI summary
An example semiconductor device includes a plurality of analog-to-digital converters (ADCs) configured to receive an analog signal from at least one amplifier connected to a pad, and a logic circuit configured to control the plurality of ADCs. The logic circuit is configured to activate first active ADCs, among the plurality of ADCs, in a first operating mode, and to activate second active ADCs, among the plurality of ADCs, in a second operating mode different from the first operating mode. A first latency required for the first active ADCs to receive the analog signal and to output a first digital signal is longer than a second latency required for the second active ADCs to receive the analog signal and to output a second digital signal.