Receiver ADC Offset Calibration for High-Speed Serial ISI
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Solution Overview
Problem
In high-speed serial communication systems, receiver devices face challenges in accurately decoding data due to inter-symbol interference (ISI) caused by transmission path characteristics, leading to offset deviations in analog-to-digital conversion, which affect reception characteristics.
Innovation Solution
The receiver device employs a digital signal processor with time-interleaved analog-to-digital converters and offset adjustment circuits to calibrate individual and common offsets in digital values, using random signal and data signal operations to adjust and stabilize the offset calibration codes, thereby compensating for offset differences and changes in transmission path characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed serial communication is implemented, then communication speed is improved, but inter-symbol interference and offset deviations occur leading to degraded reception characteristics
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before actual data reception. The receiver device executes calibration operations using test signals to determine offset calibration codes in advance, then applies these codes during normal operation to prevent offset deviations from degrading reception characteristics
Solution Approach 2:
The patent implements feedback mechanisms where the receiver device continuously monitors reception characteristics and adjusts offset calibration codes accordingly. The digital signal processor analyzes received signals and modifies calibration parameters to maintain optimal performance despite transmission path variations
2Manufacturing precision
If offset calibration is performed individually for each converter, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the calibration process into distinct stages: individual converter calibration followed by common calibration. This segmented approach allows each converter to be calibrated independently for high precision while managing overall system complexity through structured procedural division
Solution Approach 2:
The patent implements universality by designing a calibration system that handles both individual converter calibration and common calibration using the same basic infrastructure. The digital signal processor and calibration circuits serve multiple functions, reducing overall device complexity while maintaining high calibration accuracy
3Reliability
If multiple calibration operations are performed, then reception characteristics are improved, but loss of time occurs during calibration processes
Solution Approach 1:
The patent applies periodic action by performing calibration operations at strategically timed intervals rather than continuously. Calibration is executed during initialization and at predetermined moments during operation, minimizing time loss while maintaining reception characteristics through periodic reinforcement of calibration parameters
Data Source
AI summary
According to one embodiment, a receiver device includes: a plurality of converters each configured to sample a digital value from an analog signal, each digital value being sampled at different timing; and a digital signal processor configured to calibrate offsets of the digital values. The plurality of converters include a first converter and a second converter. The digital signal processor is configured to: calibrate a first offset caused in the first converter and a second offset caused in the second converter, in a first operation using a first analog signal; and calibrate a third offset that is caused commonly in the first converter for which the first offset is calibrated and the second converter for which the second offset is calibrated, in a second operation using a second analog signal.