Receiver Architecture Using Analog FFT for GHz Bandwidth
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Solution Overview
Problem
Conventional receivers face limitations in achieving a GHz operating bandwidth due to high production complexity and costs, particularly with high-speed ADCs required for direct RF receivers.
Innovation Solution
A receiver architecture incorporating a high-speed sampling module, an analog Fast Fourier Transform (AFFT) module, a selection switch module, and a low-speed ADC module, which performs time-to-frequency conversion and selects the analog frequency domain signal with the minimum center frequency for analog-to-digital conversion, avoiding the need for high-speed ADCs and frequency mixers or I/Q demodulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed ADC with high sampling bandwidth is used in a direct RF receiver to achieve GHz operating bandwidth, then the operating bandwidth reaches GHz magnitude, but the production complexity and costs become extremely high
Solution Approach 1:
The receiver is divided into multiple functional modules: a first down-converter for initial frequency conversion, a second down-converter for further frequency conversion, and a low-speed ADC. This segmentation allows each module to operate at lower speeds individually while achieving GHz bandwidth through coordinated operation, avoiding the need for a single high-speed ADC.
Solution Approach 2:
The patent introduces intermediate frequency conversion stages (first and second down-converters) as mediators between the RF signal and the low-speed ADC. These intermediaries progressively reduce the signal frequency before digital conversion, enabling the use of low-speed ADCs while maintaining GHz operating bandwidth capability.
2Speed
If a high-speed ADC with high sampling bandwidth is used in a direct RF receiver to achieve GHz operating bandwidth, then the operating bandwidth reaches GHz magnitude, but the costs become extremely high
Solution Approach 1:
The receiver is divided into multiple functional modules: a first down-converter for initial frequency conversion, a second down-converter for further frequency conversion, and a low-speed ADC. This segmentation allows each module to operate at lower speeds individually while achieving GHz bandwidth through coordinated operation, avoiding the need for a single high-speed ADC.
Solution Approach 2:
The patent introduces intermediate frequency conversion stages (first and second down-converters) as mediators between the RF signal and the low-speed ADC. These intermediaries progressively reduce the signal frequency before digital conversion, enabling the use of low-speed ADCs while maintaining GHz operating bandwidth capability.
3Device complexity
If conventional frequency mixers or I/Q demodulators are used, then the receiver structure is established, but the channel bandwidth limitation prevents operating bandwidth from reaching GHz magnitude
Solution Approach 1:
The patent employs dynamically adjustable sampling rates in the ADC and corresponding adjustable Fast Fourier Transform (FFT) processing. The sampling rate can be adapted to different operating conditions, and the FFT size can be adjusted to optimize performance, enabling the receiver to achieve GHz bandwidth while maintaining flexibility in handling different signal conditions.
Solution Approach 2:
The system changes key parameters including sampling rate, FFT size, and frequency conversion stages to overcome the bandwidth limitations of conventional mixers and demodulators. By adjusting these parameters, the receiver achieves GHz operating bandwidth while using lower-cost, lower-complexity components.
Data Source
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Figure 5(A)~5(C)
AI summary
Embodiments of the present invention disclose a receiver, including a high-speed sampling module (110), an analog Fast Fourier Transform (AFFT) module (120), a selection switch module (130), a low-speed analog to digital converter (ADC) module (140), and a control module (150). The high-speed sampling module (110) is configured to sample a received signal and output a sampled signal to the AFFT module (120); the AFFT module (120) is configured to perform time-to-frequency conversion on the sampled signal and output an analog frequency domain signal to the selection switch module (130); the selection switch module (130) is configured to transmit the analog frequency domain signal to the low-speed ADC module (140); the low-speed ADC module (140) is configured to convert the analog frequency domain signal to a digital baseband signal; and the control module (150) is configured to perform configuration on a sampling rate of the high-speed sampling module (110), a quantity of points of Fast Fourier Transform that are used by the AFFT module (120) for performing time-to-frequency conversion, and a target input port of the selection switch module (130). Correspondingly, the embodiments of the present invention further disclose a signal processing method. According to the present invention, an operating bandwidth of the receiver can reach a GHz magnitude, and the receiver has advantages such as low costs and low complexity.