Receiver Clock Lane Bias Control for Low-Power MIPI Mode Switching
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Solution Overview
Problem
Existing receiver circuits based on the MIPI protocol face challenges in reducing power consumption, especially when changing power modes, which can lead to increased power consumption and potential skew between clock and data lane modules.
Innovation Solution
The proposed receiver circuit includes data lane modules, a clock lane module, a bias current controller, and a link layer. The bias current controller adjusts the clock bias current based on power modes, and the link layer provides bias control signals and clock gating signals to optimize power usage. In specific power modes, the clock bias current is either cut off, set to a first magnitude, or increased to a second magnitude, allowing the circuit to operate efficiently in different power conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the power mode of the reception device is changed to operate in high speed mode, then the processing capability and data transmission speed are improved, but the power consumption is increased
Solution Approach 1:
The receiver circuit dynamically adjusts its operating state by switching between different power modes (first, second, and third power modes) based on the received signal characteristics. The bias current controller modifies the bias current magnitude according to the operational requirements, enabling the circuit to adapt its power consumption and performance levels dynamically rather than operating at a fixed state.
Solution Approach 2:
The invention changes the bias current parameter provided to the clock lane module based on different power modes. In the second power mode, a first magnitude of bias current is provided, while in the third power mode, a second magnitude (different from the first) is provided. This parameter adjustment allows the circuit to optimize between power consumption and performance by selecting appropriate current levels for different operational scenarios.
2Reliability
If the bias current is increased to improve signal reception quality in high speed mode, then the reliability is improved, but the power consumption is increased
Solution Approach 1:
The bias current controller adjusts the bias current parameter based on the determined power mode and received signal characteristics. The system provides different magnitudes of bias current (first magnitude in second power mode, second magnitude in third power mode) to optimize signal reception quality while adapting power consumption to actual operational needs rather than maintaining a constant high current level.
Solution Approach 2:
The system dynamically determines the appropriate power mode based on received signal analysis and adjusts the bias current accordingly. This dynamic adaptation allows the circuit to maintain reliable signal reception when needed while reducing power consumption during lower-demand operational phases.
Data Source
AI summary
A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals and low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.