Differential Receiver Feedback Loops for Bias and Offset Drift

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Solution Overview

Problem

Conventional receiver circuits in hard disk drives face performance degradation due to changes in drive characteristics over time, such as input referred 1/f noise, aging, and temperature/voltage variations, which are not accommodated by fixed programmed requirements, leading to potential system failure and yield loss, especially exacerbated by CMOS technology.

Innovation Solution

The implementation of a receiver circuit with two conjoined feedback loops that track and correct for time-related variations in input voltage bias levels and output referred offset voltages, using low-pass filters to attenuate noise and center differential outputs around a common mode voltage, preventing saturation and ensuring optimal signal processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional receivers use manual programming for fixed input bias voltage and gain levels, then the circuit design is simple, but the performance degrades over time due to aging, temperature, and voltage variations

Engineering Contradiction:
Improveperformance stabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements automatic bias voltage adjustment through feedback mechanisms that continuously monitor and adapt the input bias voltage based on actual operating conditions, eliminating the need for manual programming and maintaining optimal performance over time

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The receiver circuit transitions from static fixed bias voltages to dynamic adaptive biasing, where the bias voltage automatically adjusts in response to temperature, voltage, and aging variations, ensuring consistent performance throughout the device lifecycle

Inventive Principle:
Principle #15Dynamics

2Ease of manufacture

If CMOS technology is used to design hard disk drives, then manufacturing cost is reduced, but 1/f noise becomes more predominant causing performance degradation

Engineering Contradiction:
Improvemanufacturing costVSAvoid1/f noise
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent acknowledges the inherent 1/f noise in CMOS technology and implements filtering and compensation mechanisms that convert this harmful effect into manageable noise levels, allowing CMOS receivers to achieve acceptable performance despite the noise characteristic

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Adaptability or versatility

If fixed programmed requirements are used in hard disk drives, then the system is simple to implement, but it cannot accommodate changes in drive characteristics over time leading to system failure

Engineering Contradiction:
Improveadaptability to changesVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The receiver circuit performs self-adjustment of bias voltages and gain levels without external intervention, automatically adapting to changing drive characteristics through built-in monitoring and correction mechanisms that eliminate the need for complex external calibration systems

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8824078B1Receiver circuits and methods for processing received signals
Publication Date: 2014.09.02 TEXAS INSTRUMENTS INC
  • US8824078B1 patent drawing
  • US8824078B1 patent drawing
  • US8824078B1 patent drawing

AI summary

Receiver circuits and methods of processing received signals are disclosed herein. An embodiment of a receiver circuit includes a differential input having a first input and a second input and a differential output having a first output and a second output. A first feedback loop is connected to the input and the output, wherein the first feedback loop centers a differential output voltage around a common mode output voltage so that the differential sum is zero centered on the common mode output voltage. The circuit also includes a second feedback loop, wherein the second feedback loop centers the voltage at the first input and the voltage at the second input to a reference voltage.