High-Speed Receiver Frontend Biasing for Duty Cycle Correction

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Solution Overview

Problem

Existing input receivers in memory devices experience duty cycle distortions due to separate duty cycle correction (DCC) circuits that increase load, reduce bandwidth, and increase power consumption, limiting high-speed data communication performance.

Innovation Solution

Analog frontend with integrated biasing circuit for adjusting common mode voltages to correct duty cycles without additional DCC circuits, maintaining bandwidth and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If separate duty cycle correction circuits are used, then duty cycle distortion is corrected, but bandwidth is reduced and power consumption increases

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidbandwidth

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent combines the duty cycle correction function with the existing biasing circuit in the analog frontend, eliminating the need for separate DCC circuits. The biasing circuit is modified to include control inputs that adjust common-mode voltages based on duty cycle error signals, thereby integrating correction functionality into the signal processing path without adding external correction stages that would limit bandwidth.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The biasing circuit is designed to perform multiple functions: establishing proper common-mode voltage levels for differential signaling and simultaneously correcting duty cycle distortions. By making the biasing circuit adjustable through duty cycle control inputs, it serves both as a voltage reference source and an active duty cycle correction mechanism, reducing overall system complexity and avoiding bandwidth penalties.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If separate duty cycle correction circuits are used, then duty cycle distortion is corrected, but power consumption increases

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent merges the duty cycle correction functionality into the existing biasing circuit, which is already powered and operational in the analog frontend. This integration eliminates the need for additional powered correction circuits, thereby correcting duty cycle distortions without increasing overall power consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The biasing circuit uses its own existing power supply and operational infrastructure to perform duty cycle correction. By leveraging the already-powered biasing network and its control mechanisms, the system achieves duty cycle correction without requiring separate power sources or additional power-hungry correction stages.

Inventive Principle:

Principle #25Self-service

3Measurement precision

If separate duty cycle correction circuits are used, then duty cycle distortion is corrected, but layout area increases

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidlayout area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent integrates duty cycle correction functionality into the existing biasing circuit structure, which occupies necessary space for its primary voltage reference function. This integration eliminates the need for separate DCC circuit blocks, thereby correcting duty cycle distortions without increasing the overall layout area of the analog frontend.

Inventive Principle:

Principle #5Merging (Combining)

4Measurement precision

If separate duty cycle correction circuits are used, then duty cycle distortion is corrected, but signal integrity is degraded

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidsignal integrity degradation

Core Design Contradiction:

Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent combines duty cycle correction with the biasing circuit operation, allowing correction to occur within the existing signal processing path rather than as a separate post-processing stage. This integration ensures that duty cycle correction does not introduce additional signal degradation that would occur with separate correction circuits adding load and complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250392297A1Duty cycle correction for high-speed receiver

Publication Date: 2025.12.25 MICRON TECHNOLOGY INC

AI summary

Methods, systems, and devices for techniques for duty cycle correction are described. The duty cycle correction can be performed for an input receiver of an input/output (I/O) circuit operable to communicate data. The input receiver comprises an analog frontend operable in a multi-giga Hertz frequency range. The analog frontend comprises an input circuit stage configured to receive analog differential input signals from external of the I/O circuit; an output circuit stage configured to provide frontend differential output signals based on the received analog differential input signals; and a biasing circuit controllable to adjust common mode voltages of the frontend differential output signals such that duty cycles of the frontend differential output signals are varied.