Receiver Circuit Bin Mapping for Fast PDSCH De-Interleaving
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Solution Overview
Problem
Current systems, particularly those using field programmable gate arrays (FPGAs), face challenges in meeting timing requirements for de-interleaving data on the Physical Downlink Shared Channel (PDSCH) in 5G communication systems, as they require significant computational resources and may not be able to reverse the interleaving process efficiently for a large number of User Equipment (UEs).
Innovation Solution
A receiver circuit configured to receive and de-interleave data by placing bits into bins of a specific width and transferring them to registers, using a data bus and Q registers, allowing for efficient handling and processing of interleaved packets, which can be implemented in software, hardware, or firmware, and stored on computer-readable media.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the de-interleaving process is performed by simply reversing the interleaver process on a per bit basis for each UE, then the implementation is straightforward and follows the specification, but the computational resources required become excessive and timing requirements cannot be met when emulating a large number of UEs
Solution Approach 1:
The patent divides the de-interleaving process into multiple parallel processing channels, one for each UE. Each channel independently processes the interleaved data for its assigned UE using the formula output_bit_index = input_bit_index mod UE_ID. This segmentation allows the system to handle multiple UEs simultaneously without overwhelming computational resources, as each segment operates independently and can be processed in parallel on FPGA hardware.
Solution Approach 2:
The patent pre-calculates and stores the de-interleaving parameters and formulas for each UE during system initialization. The mapping relationships and modulation-specific parameters are prepared in advance, allowing the actual de-interleaving operation to proceed efficiently without real-time computation overhead. This preliminary preparation enables the system to meet timing requirements by eliminating complex runtime calculations.
2Adaptability or versatility
If test systems use FPGAs to emulate multiple UEs, then the system can handle multiple users simultaneously, but the timing requirements cannot be met due to the significant computational resources required for de-interleaving
Solution Approach 1:
The system segments the multi-UE processing into independent parallel channels, where each FPGA resource handles a specific UE's de-interleaving task. This allows simultaneous processing of multiple UEs without sequential overhead, maintaining adaptability for different numbers of UEs while reducing processing time through parallel execution.
Solution Approach 2:
The patent applies different de-interleaving parameters and formulas based on the specific UE ID and modulation type. By changing the parameters dynamically according to the target UE and modulation scheme (QPSK, 16QAM, 64QAM, 256QAM), the system maintains versatility for different configurations while optimizing processing speed for each specific case.
3Reliability
If the de-interleaving is performed using the standard method outlined in 3GPP TS for each UE, then the implementation is specification-compliant, but the process requires significant computational resources that FPGAs cannot provide within timing constraints
Solution Approach 1:
The patent maintains specification compliance by implementing the exact de-interleaving formula output_bit_index = input_bit_index mod UE_ID for each UE, as required by 3GPP TS. The segmentation into parallel UE-specific channels allows this compliant implementation to scale efficiently, with each segment processing its assigned UE independently, thereby maintaining both reliability through spec compliance and productivity through parallel processing.
Solution Approach 2:
The system prepares all necessary de-interleaving parameters, formulas, and mapping relationships in advance according to 3GPP specifications. This preliminary setup ensures specification compliance is built into the hardware logic itself, eliminating the need for complex runtime computations and enabling high-throughput processing that meets both reliability and productivity requirements.
Data Source
AI summary
A system includes a data bus, Q registers each having a register width B, and a receiver circuit. The receiver circuit is configured for receiving, at each clock cycle of a number of clock cycles of the communication system, a bit lane of data on a data bus, each bit lane including Q valid bits of an interleaved packet of length E. The receiver circuit is configured for placing, at each clock cycle, each of the Q valid bits into a respective bin of Q bins each having a bin width equal to the register width B. The receiver circuit is configured for determining that the bins are full, and in response to determining that the bins are full, transferring the contents of the bins into the registers.