Receiver Chip BIST Using Frequency Control Circuit
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Solution Overview
Problem
Integrating built-in self-test (BIST) functionality into receiver chips is challenging due to area and design resource constraints, and external testing increases costs and is limited to package level rather than wafer level.
Innovation Solution
A data receiver device with a logic unit, system frequency control circuit, and input/output terminals that can operate in test mode to generate and compare test patterns, and use an integrated frequency control circuit to perform BIST without additional design blocks, enabling both package and wafer level testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transmitter including PLL, serializer, and output driver is mounted in the receiver chip to achieve BIST functionality, then BIST capability is obtained, but chip area and design resources increase significantly
Solution Approach 1:
The receiver chip's existing frequency control circuit is made multi-functional by enabling it to operate in both normal receiver mode and test mode. In test mode, the same circuit generates test patterns and performs self-testing, eliminating the need for separate transmitter BIST components. This universal approach allows one circuit to serve multiple purposes: signal reception during normal operation and self-testing during test operation.
Solution Approach 2:
The receiver chip performs self-testing using its own internal resources without requiring external transmitter components. The frequency control circuit generates test patterns, serializes them, transmits them through the output driver, and the receiver deserializes and compares them to detect faults. This self-service mechanism eliminates dependency on external equipment for testing.
2Device complexity
If transmitter is installed external to the receiver chip for BIST testing, then additional design blocks are avoided, but testing is limited to package level and cost increases in mass production
Solution Approach 1:
The receiver chip performs self-testing using its own internal resources without requiring external transmitter components. The frequency control circuit generates test patterns, serializes them, transmits them through the output driver, and the receiver deserializes and compares them to detect faults. This self-service mechanism eliminates dependency on external equipment for testing.
Solution Approach 2:
The receiver chip is designed with the capability to perform tests before final packaging and assembly. By implementing BIST functionality within the chip itself, testing can be conducted at the wafer level prior to packaging, enabling early detection of defects and reducing the need for subsequent package-level testing with external equipment.
3Reliability
If traditional BIST implementation is used in receiver chips, then testing capability is achieved, but chip area and design resources are excessively consumed
Solution Approach 1:
The receiver chip's existing frequency control circuit is made multi-functional by enabling it to operate in both normal receiver mode and test mode. In test mode, the same circuit generates test patterns and performs self-testing, eliminating the need for separate transmitter BIST components. This universal approach allows one circuit to serve multiple purposes: signal reception during normal operation and self-testing during test operation.
Data Source
AI summary
A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit.