Receiver CDR and Serial-to-Parallel Converter for Bufferless Loop Testing
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Solution Overview
Problem
Conventional loop testing methods for receivers require additional buffers in both transmitters and receivers, increasing circuit complexity, power consumption, and design difficulty, while also complicating control processes and requiring more rigid test signal patterns.
Innovation Solution
A receiver with a CDR circuit, serial-to-parallel converter, and test module that converts serially inputted multi-bit test signal groups into parallel test bytes and compares adjacent bytes to ensure data integrity, reducing the need for multiple buffers and simplifying circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional loop testing method uses multiple buffers in transmitter and receiver to store test signal patterns, then testing accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the test signal processing function from the conventional buffer-based approach. Instead of storing complete test signal patterns in buffers, the system extracts only the essential comparison function by comparing current received data with previously received data directly, eliminating the need for complex buffer storage structures while maintaining testing accuracy
Solution Approach 2:
The patent discards the conventional approach of storing test patterns in buffers and recovers the testing function through a different mechanism: continuously comparing current received data with previous data. This discards the buffer storage concept but recovers the essential testing capability through direct data comparison, reducing device complexity while maintaining accuracy
2Reliability
If conventional loop testing method uses multiple buffers to store test patterns, then testing completeness is improved, but power consumption increases
Solution Approach 1:
The patent implements continuous data comparison without the need to load and store test patterns in buffers. The receiver continuously compares current received data with previous data in real-time, maintaining testing completeness through continuous operation rather than batch processing, which reduces power consumption by eliminating buffer management overhead
Solution Approach 2:
The system uses the received data itself for comparison purposes without requiring external test pattern storage. Each received data sequence serves as both the test input and the reference for comparison, making the system self-sufficient and eliminating the need for power-consuming buffer storage operations
3Adaptability or versatility
If conventional loop testing method adds buffers in transmitter and receiver, then testing capability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent makes the receiver capable of performing multiple functions: normal data reception and test signal comparison using the same data path and comparison logic. The receiver structure remains universal and can handle both regular communication and testing without requiring separate dedicated test hardware, improving ease of manufacture while maintaining testing capability
Solution Approach 2:
Instead of adding test hardware to the transmitter as in conventional methods, the patent inverts the approach by implementing the comparison function in the receiver. This reversal simplifies the transmitter design and makes the system easier to manufacture, as the receiver already has the necessary data processing capabilities for comparison
4Measurement precision
If conventional loop testing uses rigid test signal patterns stored in buffers, then testing accuracy is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements a dynamic testing approach where the comparison reference is continuously updated with newly received data. Instead of using fixed rigid test patterns, the system dynamically adapts by comparing current data with the most recent previous data, maintaining testing accuracy while providing flexibility to handle various data types and communication conditions
Data Source
AI summary
A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.