Multi-Level Receiver Circuit Using Averaged DFE Compensation

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Solution Overview

Problem

Existing receiver circuits in semiconductor systems face challenges in accurately receiving and decoding multi-level signals due to inter-symbol interference (ISI), which affects communication reliability between semiconductor apparatuses.

Innovation Solution

The proposed receiver circuit includes a compensation signal generation circuit, a sampling circuit, and an output circuit, which equalize input signal pairs with offsets, average voltage levels, and compare them with reference voltages to generate reception symbols, thereby mitigating ISI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If multi-level signal transmission is used to transmit more information, then information transmission capacity is improved, but inter-symbol interference increases affecting reception accuracy

Engineering Contradiction:
Improveinformation transmission capacityVSAvoidreception accuracy
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The received signal is segmented into multiple components through summing circuits that separate different voltage level ranges. Each summing circuit processes a specific segment of the multi-level signal, converting it to a standardized compensation signal pair. This segmentation allows the complex multi-level signal to be handled in manageable parts, reducing interference while preserving information capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Compensation signal pairs serve as intermediary representations between the received multi-level signal and the final decoded data. The compensation signal pairs act as mediators that standardize different voltage levels into uniform signal representations, facilitating accurate sampling and decoding while mitigating inter-symbol interference effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If multiple summing circuits and averaging circuits are added to reduce inter-symbol interference, then reception accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvereception accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Different summing circuits are configured with specific offset values tailored to their respective signal segments. Each circuit applies localized compensation appropriate to its processing range, allowing precise handling of different voltage levels without requiring uniform complex processing across the entire signal range. This local optimization achieves high accuracy while controlling overall complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The circuit transforms the multi-level signal parameters into standardized compensation signal pairs through controlled parameter changes in the summing circuits. By adjusting offset parameters and voltage level mappings, the system converts complex multi-level parameters into simpler, standardized forms that are easier to process with minimal additional complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250119138A1Receiver circuit, a semiconductor apparatus and a semiconductor system including the receiver circuit
Publication Date: 2025.04.10 SK HYNIX INC
  • US20250119138A1 patent drawing
  • US20250119138A1 patent drawing
  • US20250119138A1 patent drawing

AI summary

A receiver circuit is configured to generate a reception symbol from a multi-level signal. The receiver circuit is configured to generate three compensation signal pairs from an input signal pair to perform a loop unrolled decision feedback equalization operation. A first summing circuit is configured to equalize the input signal pair with a first offset to generate a first compensation signal pair, and a second summing circuit is configured to equalize the input signal pair with a second offset to generate a second compensation signal pair. An averaging circuit is configured to average the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair.