Receiver Circuit Noise-Induced Mode Transition Prevention
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Solution Overview
Problem
The MIPI-DSI standard-based communication systems face issues with noise-induced incorrect mode transitions, leading to undesired halts in high-speed data communication modes, as the receiving-side circuit may mistakenly switch from HS mode to LP mode due to noise on the clock lane, causing data communication failures.
Innovation Solution
A receiver circuit configuration that includes a mode detection circuit, clock generator circuit, data reception circuits, and a malfunction detection circuit to accurately identify communication modes and prevent incorrect mode transitions by asserting an HS-mode return signal when a malfunction is detected, ensuring the clock lane remains in the HS mode until data transmission is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the receiving-side circuit detects mode transitions based on clock lane voltage levels, then the communication mode can be switched between HS and LP modes, but noise on the clock lane may cause incorrect mode detection leading to undesired halts in HS mode
Solution Approach 1:
The malfunction detection circuit continuously monitors the clock lane signal and provides feedback to detect incorrect mode transitions. When noise causes a false LP mode detection during HS mode operation, the feedback mechanism identifies this malfunction and triggers a correction by resetting the mode detection circuit to maintain proper HS mode operation.
Solution Approach 2:
The malfunction detection circuit acts as an intermediary between the mode detection circuit and the communication system. It monitors the clock lane signal independently and intervenes when incorrect mode detection occurs, preventing the undesired halt of data communication by coordinating with the mode detection circuit to maintain correct mode operation.
2Use of energy by moving object
If the clock generator circuit halts internal clock signal generation in LP mode, then power consumption is reduced, but communication speed decreases
Solution Approach 1:
The clock generator circuit dynamically adjusts its operation based on the detected communication mode. In HS mode, it generates the internal clock signal at high speed to enable fast data transmission. When transitioning to LP mode, it halts clock signal generation to reduce power consumption. The system dynamically switches between these two operational states based on real-time mode detection.
3Ease of operation
If the receiver circuit uses voltage level detection on clock lane for mode transition, then mode switching is achieved, but noise susceptibility increases causing communication failures
Solution Approach 1:
The malfunction detection circuit is positioned to detect potential mode transition errors before they cause communication failures. By continuously monitoring the clock lane signal and comparing detected transitions with expected patterns, it identifies noise-induced false detections early and initiates correction procedures to prevent communication breakdown.
Solution Approach 2:
The system implements a feedback loop where the malfunction detection circuit monitors the clock lane signal and provides correction signals to the mode detection circuit when noise causes incorrect mode detection. This feedback mechanism ensures that transient noise spikes do not result in permanent mode switching errors.
Data Source
AI summary
A receiver circuit includes a CLK_LP circuit, a CLK_HS circuit, a DATA_LP circuit, a DATA_HS circuit and a malfunction detection circuit. The CLK_LP circuit and the CLK_HS circuit are connected to the clock lane. The DATA_LP circuit and the DATA_HS circuit are connected to the data lane. The malfunction detection circuit is configured to assert an HS-mode return signal when a first mode signal indicating the communication mode of the clock lane is set to the LP mode at a moment when the second mode signal indicating the communication mode of the data lane is switched from the HS mode to the LP mode. The CLK_LP circuit sets the first mode signal to the HS mode in response to the assertion of the HS-mode return signal.