Receiver Circuit Skew Mitigation via Data Comparison
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Solution Overview
Problem
Long transmission distances lead to significant skew between data and clock signals in semiconductor chip circuits, making it difficult to design flip-flop circuits that can receive data at the same timing, especially at higher operating frequencies.
Innovation Solution
The receiver circuit employs a configuration with first and second holding circuits, a comparison circuit, and logical circuits to synchronize and compare reception data, ensuring identical data latching and output even when data transition timings differ, thereby reducing the need for stringent timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the transmission distance is increased, then the data transfer capability is improved, but the skew between data and clock signals becomes large making it difficult to satisfy timing constraints
Solution Approach 1:
The data transmission is divided into multiple segments (data groups) that are transmitted in parallel through different paths. Each segment can be independently timed and synchronized, allowing the system to handle long transmission distances by breaking them into manageable portions that can be synchronized at the receiver end.
Solution Approach 2:
The system performs preliminary synchronization by using the clock signal to pre-align the timing of data groups before they are latched by the flip-flop circuits. This preliminary timing adjustment ensures that even after long transmission distances cause skew, the data arrives at the latch in a synchronized state.
2Productivity
If the operating frequency is increased, then the productivity is improved, but the timing constraints become more stringent making it difficult to design transmission circuits
Solution Approach 1:
The system uses feedback mechanisms where the clock signal, which is distributed to all flip-flop circuits, serves as a reference for timing alignment. The synchronized latching of data groups based on this common clock reference creates a feedback loop that maintains timing consistency even at high operating frequencies, reducing the complexity of manual timing constraint design.
Solution Approach 2:
The invention changes the timing parameter relationship by using edge-triggered flip-flop circuits that latch data on specific clock edges. This parameter change from level-triggered to edge-triggered operation allows for more relaxed timing constraints while maintaining high operating frequencies, as the precise moment of data capture is determined by the clock edge rather than continuous level monitoring.
3Productivity
If multiple data signals are transmitted in parallel, then the data transfer efficiency is improved, but the skew between different data paths increases making simultaneous reception difficult
Solution Approach 1:
The system creates equipotential timing conditions by using a common clock signal distributed to all flip-flop circuits in parallel. This ensures that all data paths, regardless of their physical length or complexity, are evaluated at the same timing reference point, effectively equalizing the timing potential across all parallel transmission paths and enabling reliable simultaneous reception.
Data Source
AI summary
A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical.