Differential Signal Receiver Circuit for Common-Mode Spike Rejection
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Solution Overview
Problem
Conventional isolated gate driver devices suffer from spurious pulses in the reconstructed signal due to common-mode ringing effects, which affect the accuracy of signal decoding across the galvanic isolation barrier, leading to unwanted commutations in high-voltage motor control applications.
Innovation Solution
A receiver circuit with an improved architecture that includes a logic circuit to detect and correct spurious pulses by generating corrected set and reset signals, using asymmetric buffer circuits and gating logic gates to filter out pulses exceeding a certain duration threshold, thereby enhancing common-mode transient immunity without requiring complex modifications to existing transmitter/receiver architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional receiver circuit architecture is used, then device complexity is low, but spurious pulses are generated due to common-mode ringing effects
Solution Approach 1:
The receiver circuit is segmented into distinct functional blocks: asymmetric buffer circuits for edge detection, gating logic gates for pulse validation, and debouncing logic for final signal stabilization. This segmentation allows each component to address specific aspects of spurious pulse rejection while maintaining overall system manageability
Solution Approach 2:
Asymmetric buffer circuits and gating logic gates are introduced as intermediary components between the differential input and the final decoded output. These intermediaries filter out spurious pulses by validating pulse duration and edge characteristics before allowing signals to pass to the output stage
2Reliability
If simple receiver architecture is used, then ease of manufacture is high, but common-mode transient immunity is poor
Solution Approach 1:
The circuit changes the parameter of pulse duration validation by comparing received pulses against a predetermined time threshold. This parameter-based filtering effectively rejects common-mode transient spikes that exceed the valid pulse duration window while maintaining immunity against genuine signals within the threshold
3Ease of operation
If conventional decoding logic is used, then device complexity is low, but spurious pulses cause unwanted commutations
Solution Approach 1:
The circuit performs preliminary validation of incoming pulses through asymmetric buffering and gating logic before the final decoding stage. This preliminary action filters out invalid pulses based on duration and edge characteristics, ensuring that only validated signals reach the decoding logic and trigger commutations
Data Source
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AI summary
A receiver circuit (104') receives a differential signal (Vd) that includes positive and negative spikes, and produces an output signal (PWMRX) as a function of the differential signal. A first comparator (42) produces an intermediate set signal (COMPN) that includes a pulse at each positive spike of the differential signal, and a second comparator (44) produces an intermediate reset signal (COMPP) that includes a pulse at each negative spike of the differential signal. A logic circuit (90) detects whether the digital signal (PWMRX) switches between a first value and a second value, and whether the intermediate reset signal (COMPP) and the intermediate set signal (COMPN) include pulses lasting longer than a threshold. The logic (90) produces a set correction signal - respectively, a reset correction signal - that includes a pulse when the digital signal (PWMRX) switches and, at the same time, the intermediate reset signal - respectively, the intermediate set signal - includes a pulse lasting longer than the threshold. The logic (90) produces a corrected set signal (COMP'N) - respectively, a corrected reset signal (COMP'P) - that includes the pulses of the intermediate set signal (COMPN) - respectively, the pulses of the intermediate reset signal (COMPP) - and the pulses of the set correction signal- respectively, the pulses of the reset correction signal. An output circuit (46) asserts the output signal (PWMRX) in response to a pulse detected in the corrected set signal (COMP'N) and de-asserts the output signal (PWMRX) in response to a pulse detected in the corrected reset signal (COMP'P).