Receiver Circuit Input Voltage Protection
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Solution Overview
Problem
As integrated circuit process geometries scale down and operating voltages decrease, there is a growing mismatch between interface and internal voltages, leading to oxide layer overstress in NMOS and PMOS devices, causing malfunction and performance degradation in receiver circuits, especially when external voltages exceed internal voltages, and existing voltage-tolerant circuits impose significant manufacturing costs or result in duty cycle distortion.
Innovation Solution
The proposed solution involves a receiver circuit with conduction path circuitry comprising a PMOS transistor and an NMOS transistor in series, connected in parallel with another PMOS transistor, and an overvoltage-reduction NMOS transistor, along with buffer circuitry that switches the second transistor to a low conductance state to block the conduction path when the input voltage reaches a certain level, and a shut-down PMOS transistor to fully switch off the first PMOS transistor when the input voltage is high, ensuring safe operation and reduced oxide layer stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interface voltage is increased to 2.7V for backward compatibility, then the receiver circuit can interface with external devices, but the oxide layer of NMOS and PMOS devices breaks down causing circuit malfunction
Solution Approach 1:
The receiver circuit is divided into multiple voltage domains: an input stage that can tolerate 2.7V and an internal core stage that operates at lower voltage (1.8V or 1.5V). The input stage includes transistors sized and configured to handle higher voltages without oxide breakdown, while the core stage uses smaller transistors optimized for lower voltage operation. This segmentation allows the circuit to interface with external 2.7V devices while protecting the sensitive internal circuitry from voltage overstress.
Solution Approach 2:
A voltage level shifting mechanism is introduced as an intermediary between the 2.7V input and the lower voltage core circuitry. This intermediary converts the high voltage input signal to a compatible lower voltage level that the core circuit can process safely, preventing direct exposure of sensitive internal transistors to overstressing voltages while maintaining backward compatibility with external devices.
2Reliability
If slow transistors are used in the signal path to ensure voltage tolerance, then the circuit can handle higher voltages, but the receiver performance is degraded with duty cycle distortion
Solution Approach 1:
The circuit is segmented into voltage-tolerant input transistors and fast core transistors. The input stage transistors are designed with larger dimensions to tolerate 2.7V operation, while the core stage transistors are optimized for speed at lower voltages. This segmentation allows each part of the circuit to be optimized for its specific function without compromising overall performance.
Solution Approach 2:
Different transistor sizes and characteristics are used in different parts of the circuit. The input stage uses larger, more robust transistors capable of withstanding higher voltages, while the core logic stage uses smaller, faster transistors optimized for high-speed operation at lower voltages. This local differentiation of transistor quality allows the circuit to achieve both voltage tolerance and high performance.
3Reliability
If additional masks are used during manufacture to create voltage tolerant circuits, then the circuit can tolerate higher voltages, but the manufacturing complexity and cost increase
Solution Approach 1:
The receiver circuit design uses standard transistor configurations and sizing that can be implemented using existing manufacturing processes without requiring additional specialized masks or process steps. The voltage tolerance is achieved through careful selection of transistor dimensions and configuration rather than through special manufacturing techniques, making the design compatible with standard CMOS fabrication processes.
Data Source
AI summary
An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16. Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16. A first NMOS transistor 28 is connected between the input 10 and the first node 16. The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.