Receiver Clock Recovery with Bias-Adaptive First-Order Loop Filter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current clock and data recovery mechanisms in receivers require high precision circuit design due to significant multiplication in second-order loop filters, leading to increased latency.
Innovation Solution
Employ a first-order loop filter circuit with a proportional path and a bias adaptation circuit to process phase errors, generating a bias value to correct frequency errors, reducing latency by eliminating the integral path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a second-order loop filter is used to track frequency and phase errors separately, then tracking accuracy is improved, but latency increases significantly
Solution Approach 1:
The patent segments the second-order loop filter into two independent first-order loop filters: one dedicated to phase error tracking and another to frequency error tracking. This segmentation allows each filter to operate independently with reduced complexity, maintaining tracking accuracy while eliminating the latency inherent in cascaded second-order filtering structures.
Solution Approach 2:
The patent introduces a phase offset signal as an intermediary that couples the frequency tracking path to the phase tracking path. This intermediary allows the frequency error corrections to be applied without requiring the signal to pass through the phase filter, thereby maintaining accuracy while reducing latency.
2Measurement precision
If the integral path processes the input signal with larger magnitude multiplication, then frequency tracking precision is improved, but circuit design complexity and latency increase
Solution Approach 1:
The patent extracts the frequency tracking function into a separate first-order loop filter that operates independently from the phase tracking filter. By taking out the integral path's frequency correction function and implementing it separately with a bias adaptation circuit, the patent achieves frequency tracking precision without requiring high-magnitude multiplication in a single complex filter.
Solution Approach 2:
The patent changes the operational parameters of the frequency tracking path by using a first-order filter with a bias adaptation circuit that accumulates phase detection signals to generate bias values. This parameter change allows frequency tracking to be achieved with simpler circuitry and lower latency compared to the traditional second-order filter with integral path.
Data Source
AI summary
A receiver includes an analog to digital converter circuit, a phase detector circuit, a digital loop filter circuit, a phase interpolator circuit, and a bias adaption circuit. The analog to digital converter circuit is configured to convert a first signal into a second signal according to a clock signal. The phase detector circuit is configured to detect a phase of the second signal to generate a phase detection signal. The digital loop filter circuit is configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal. The phase interpolator circuit is configured to generate the clock signal according to the third signal. The bias adaptation circuit is configured to accumulate the phase detection signal to generate the bias value.