Receiver Multi-Phase Clock Calibration via Duty-Cycle Correction
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Solution Overview
Problem
Existing multi-phase clock calibration techniques in receivers are sensitive to integral non-linearity of delay circuits, leading to inaccuracies in aligning decision circuits with the center of the data eye, which affects symbol error rates in high-speed communications.
Innovation Solution
A calibration circuit that adjusts the multi-phase clock by manipulating clock duty cycles and phases to align decision circuits with the center of the data eye, converting integral non-linear errors into quantization errors for improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional multi-phase clock calibration is used, then the calibration process is simple, but the precision is degraded due to sensitivity to integral non-linearity of delay circuits
Solution Approach 1:
The patent introduces reference voltages as an intermediary element between the decision circuits and the clock calibration process. By comparing received signal amplitudes to reference voltages and using the comparison results to adjust clock phases, the system achieves higher calibration precision without directly relying on delay circuit linearity. The reference voltages act as a mediator that converts the calibration problem into a voltage comparison task, thereby reducing sensitivity to delay circuit integral non-linearity.
2Measurement precision
If delay circuits are used to align clocks with data eye center, then the alignment can be achieved, but the accuracy is degraded due to integral non-linearity
Solution Approach 1:
The patent converts the harmful effect of integral non-linearity in delay circuits into a beneficial calibration mechanism. Instead of trying to eliminate the non-linearity, the system uses reference voltage comparisons to detect and compensate for timing errors. The non-linear delay characteristics are transformed into measurable voltage differences that can be corrected through feedback control, turning a source of error into a calibration signal.
Solution Approach 2:
The patent implements a feedback mechanism where decision circuit comparison results are used to adjust clock phases. The reference voltages and decision circuits continuously monitor the alignment between clock edges and data eye centers, and the calibration circuit uses this feedback information to iteratively refine clock timing. This closed-loop feedback system compensates for delay circuit non-linearities by continuously correcting clock phases based on actual performance measurements.
Data Source
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AI summary
An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.