Receiver Multi-Phase Clock Calibration Using Duty-Cycle Correction
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Solution Overview
Problem
Existing multi-phase clock calibration techniques in receivers are sensitive to integral non-linearity of delay circuits, leading to inaccurate alignment of decision circuits within the data eye, which affects symbol recovery accuracy.
Innovation Solution
A calibration circuit that adjusts the multi-phase clock by manipulating duty-cycle and phase relationships of component clocks, using feedback from decision circuits to center the clock comparisons at the data eye center, converting integral non-linear errors into quantization errors for improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional multi-phase clock calibration is used, then the calibration process is simple, but the alignment precision of decision circuits is degraded due to sensitivity to integral non-linearity of delay circuits
Solution Approach 1:
The patent implements a feedback mechanism where the calibration circuit receives alignment information from decision circuits and adjusts duty cycles accordingly. The system measures the actual alignment error and uses this feedback to iteratively improve the clock phase alignment, converting integral non-linear errors into quantization errors that can be corrected through feedback control.
Solution Approach 2:
The patent changes the duty cycle parameter of the multi-phase clocks as the primary calibration variable. By adjusting duty cycles rather than relying solely on delay circuit tuning, the system can compensate for integral non-linearity effects and achieve more precise alignment of decision circuits with the data eye center.
2Reliability
If duty cycle correction is applied to improve alignment precision, then symbol error rate decreases, but calibration circuit complexity increases
Solution Approach 1:
The patent introduces a calibration circuit as an intermediary component that mediates between the clock distribution network and decision circuits. This intermediary performs duty cycle adjustment and provides alignment information, isolating the complexity of precision alignment from the core data recovery function while improving symbol error rate.
Solution Approach 2:
The calibration function is segmented into distinct operations: measuring alignment error, generating duty cycle correction signals, and applying corrections to individual clock phases. This segmentation allows the system to achieve high precision alignment through modular, manageable steps rather than requiring a monolithic complex calibration mechanism.
Data Source
AI summary
An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.