Receiver Clock Delay Circuit for Source-Synchronous Jitter Correlation
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Solution Overview
Problem
Source-synchronous communication systems face issues with jitter amplification due to propagation delay time differences between clock and data channels, leading to loss of correlation and sampling errors, with existing solutions either filtering out useful correlation or consuming significant power and chip area.
Innovation Solution
A communication system with a receiver featuring a delay circuit that extracts and delays jitter signals from the clock channel to generate a receiver clock signal, reestablishing correlation between clock and data signals by matching propagation delays, and using a high pass filter to selectively address high-frequency jitter effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a PLL is introduced in the clock path at the receiver to filter out high-frequency jitter, then noise in the frequency band where negative correlation can appear is cut off, but all correlation information above the PLL bandwidth is lost
Solution Approach 1:
The jitter compensation is segmented into two independent parts: a feedforward path that processes the clock signal through a delay element matched to the data path delay, and a feedback path that uses a PLL to filter residual jitter. This segmentation allows different frequency components to be handled differently, preserving correlation information while suppressing harmful jitter.
Solution Approach 2:
A delay element is introduced as an intermediary component in the feedforward path, matching the propagation delay of the data path. This intermediary element pre-compensates for the delay difference between clock and data paths, allowing the correlation information to be preserved before the signal reaches the PLL stage.
2Reliability
If a high-precision delay line is used to delay the received clock signal by the actual clock-to-data skew, then timing correlation is restored, but a large amount of power and chip area is consumed and it suffers from power supply noise
Solution Approach 1:
The delay line is made dynamically adjustable rather than fixed, allowing the delay amount to be adapted based on operating conditions. This dynamic adjustment enables the system to achieve timing correlation with minimal delay compensation, reducing power consumption and chip area while maintaining reliability.
Solution Approach 2:
The delay parameter of the delay line is changed adaptively based on the actual skew conditions. By adjusting the delay parameter dynamically, the system achieves optimal timing correlation without requiring a large fixed delay line, thereby reducing power consumption and chip area usage.
3Reliability
If the clock channel is made shorter than the data channel, then propagation delay difference is reduced, but routing flexibility and board layout options are limited
Solution Approach 1:
Delay elements are introduced as intermediary components in the clock path to match the propagation delay of the data path. These intermediary elements provide the necessary delay adjustment without requiring the clock channel to be physically longer, thus maintaining routing flexibility while achieving delay matching.
Solution Approach 2:
The electrical characteristics of the clock channel are changed by adding delay elements, effectively increasing the propagation delay of the clock path to match the data path. This parameter change allows delay matching to be achieved through circuit design rather than physical routing adjustments, preserving layout flexibility.
Data Source
AI summary
The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.