Receiver Sampling Clock Synchronization for Jitter Reduction
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Solution Overview
Problem
Communication systems using the plesiochronous transmission method experience sinusoidal jitter and increased bit error rates due to frequency differences between clock signals at the receiver and transmitter, degrading clock and data recovery performance.
Innovation Solution
A receiver with a detection circuit and sampling clock generator, including a frequency synthesizer with a sigma-delta modulator and phase-locked loop, is used to detect frequency differences and generate a reception sampling clock signal that synchronizes with the transmission sampling clock signal, reducing jitter noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the receiver uses a clock signal with a different frequency from the transmitter, then the receiver can operate independently with its own clock, but sinusoidal jitter occurs and bit error rate increases
Solution Approach 1:
The patent implements a feedback mechanism where the receiver detects the frequency difference between its local clock signal and the transmitter's clock signal, then uses this detection to generate a control signal that adjusts the local clock frequency. This closed-loop feedback system continuously corrects the frequency mismatch, eliminating sinusoidal jitter and reducing bit error rate while maintaining independent operation capability.
Solution Approach 2:
The patent dynamically changes the frequency parameter of the receiver's local clock signal based on detected frequency differences. By adjusting the clock frequency in response to the detected mismatch, the system transforms from a static independent operation mode to a dynamic adaptive mode that maintains synchronization without sacrificing operational independence.
2Reliability
If frequency adjustment mechanisms are added to synchronize clock signals, then bit error rate decreases, but device complexity increases
Solution Approach 1:
The patent enables the receiver to automatically detect and correct its own clock frequency mismatch without requiring complex external synchronization equipment. The self-service mechanism uses the existing data signal and local clock to generate frequency difference detection, eliminating the need for additional sophisticated hardware while maintaining low bit error rate.
Solution Approach 2:
The patent adjusts the clock frequency parameter dynamically based on simple frequency difference detection, avoiding the need for complex fixed-frequency adjustment mechanisms. This parameter-based approach simplifies the overall circuit design compared to traditional hardware synchronization methods.
Data Source
AI summary
A receiver may include a clock and data recovery circuit, a detection circuit and a sampling clock generator. The clock and data recovery circuit may receive first data and sample the first data to generate recovered data in response to a reception sampling clock signal. The detection circuit may detect a frequency difference between a transmission sampling clock signal and the reception sampling clock signal by comparing the first data and the reception sampling clock signal to generate a frequency difference detection signal. The sampling clock generator may generate the reception sampling clock signal based on the frequency difference detection signal and a first reference clock signal. Therefore, a communication system including the receiver may effectively reduce a jitter noise.