Time-Interleaved Receiver Clock Phase Adjustment via ISI Feedback
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Solution Overview
Problem
Clock timing skew occurs in time-interleaved receivers due to manufacturing variations, leading to performance degradation, and existing methods fail to effectively detect and address this issue.
Innovation Solution
A method is implemented in a time-interleaved receiver that generates multiple clocks with the same frequency but different phases, determines intersymbol interference (ISI) values for each clock, and adjusts the clock phase based on these values to mitigate timing skew by comparing them to a reference ISI value, either the average or a specific clock's ISI value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time interleaving is used to increase sampling rate, then productivity is improved, but manufacturing precision deteriorates due to clock timing skew
Solution Approach 1:
The patent implements a feedback mechanism where ISI values are measured for each clock phase and used to adjust the clock phases iteratively. The system continuously monitors the ISI values and adjusts the clock timing based on the measured deviations, creating a closed-loop control system that compensates for manufacturing variations and maintains precise timing relationships.
Solution Approach 2:
The patent changes the clock phase parameters dynamically by adjusting the phase of each clock based on its measured ISI value. This allows the system to adapt the timing parameters in real-time to compensate for manufacturing variations, transforming fixed manufacturing precision issues into adjustable operational parameters.
2Productivity
If multiple clock generators are used for time interleaving, then productivity is improved, but reliability deteriorates due to timing skew from manufacturing variations
Solution Approach 1:
The system uses feedback by measuring ISI values for each clock and using these measurements to adjust the clock phases. This continuous monitoring and adjustment ensures that timing accuracy is maintained despite using multiple independent clock generators, thereby improving reliability while maintaining high productivity.
Solution Approach 2:
The system performs self-adjustment by automatically measuring its own ISI values and correcting its own clock timing skew without external intervention. This self-service capability allows the system to compensate for manufacturing variations inherent in multiple clock generators, maintaining reliable operation.
3Manufacturing precision
If clock phases are adjusted to correct timing skew, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the existing ISI measurement circuitry serve dual purposes: its original function of detecting intersymbol interference and the additional function of measuring clock timing skew. By using the same hardware infrastructure for both purposes, the system avoids adding dedicated complexity for skew measurement while still achieving precise clock alignment.
Data Source
AI summary
Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.