Serial Data Receiver Clock Phase Alignment for Sampling Margin
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Solution Overview
Problem
Existing reception apparatuses face challenges in securing an operating margin between serial data signals and sampling clock signals due to the large variation in delay time caused by multistage delay gate circuits, making it difficult to receive high-speed serial data signals effectively.
Innovation Solution
A reception apparatus comprising a sampler block circuit, a phase adjustment circuit, and a sampling clock signal generation circuit, where the phase adjustment circuit adjusts the clock signal phase to cancel out the delay time, ensuring the sampling clock signal is synchronized with the serial data signal, thereby securing an operating margin between the signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multistage delay gate circuit is used to delay serial data signals, then the sampling timing can be adjusted to the center of the data window, but the delay time variation becomes large and transition time increases
Solution Approach 1:
Instead of delaying the serial data signal through multiple delay gates, the invention inverts the approach by delaying the sampling clock signal through a single delay element. This clock delay achieves the same timing alignment function while avoiding the problems of data signal degradation and large delay variation associated with multistage delay circuits.
Solution Approach 2:
The invention extracts the delay function from the data signal path and relocates it to the clock signal path. By removing the delay circuit from the data signal flow and placing it only in the clock signal flow, the system achieves timing adjustment without subjecting the fast-changing data signals to multiple gate transitions.
2Measurement precision
If the number of gate stages in the delay circuit is increased to achieve precise sampling timing, then the transition time for data signal level changes increases, but this reduces the operating margin between data signals and sampling clock
Solution Approach 1:
The invention inverts which signal is delayed: instead of delaying data through multiple gates (which increases transition time), it delays the clock through a single element. This maintains fast data signal transitions while achieving precise sampling timing, thereby preserving both accuracy and high-speed reception capability.
3Measurement precision
If a delay circuit is added before the sampler block circuit to adjust sampling timing, then the sampling timing can be centered on the data window, but the device complexity and power consumption increase
Solution Approach 1:
The invention merges the delay function into the existing clock distribution path rather than adding a separate delay circuit in the data path. The delay element is integrated into the clock signal flow that already reaches the sampler block, combining timing adjustment with the existing clock distribution infrastructure.
Solution Approach 2:
By inverting which signal receives the delay (clock instead of data), the invention eliminates the need for complex multistage delay circuits in the data path. A single delay element in the clock path suffices, significantly reducing device complexity while achieving the same timing alignment.
Data Source
AI summary
In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.